Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FCVTMU (scalar, H to W)

Test 1: uops

Code:

  fcvtmu w0, h0
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 3.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 2.000

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst int alu (97)l1d cache writeback (a8)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
200454140642530001000200020001800005225415412483274200020002000541541111001100007311611538100010001000542542542542542
200454140432530001000200020001800005225415412483274200020002000541541111001100007311611538100010001000542542542542542
200454140432530001000200020001800005225415412483274200020002000541541111001100007311611538100010001000542542542542542
200454140432530001000200020001800005225415412483274200020002000541541111001100017311611538100010001000542542542542542
200454140432530001000200020001800005225415412483274200020002000541541111001100007311611538100010001000542542542542542
200454140432530001000200020001800005225415412483274200020002000541541111001100007311611538100010001000542542542542542
2004541412432530001000200020001800005225415412483274200020002000541541111001100007311611538100010001000542542542542542
2004541401152530001000200020001800005225415412483274200020002000541541111001100007311611538100010001000542542542542542
200454140432530001000200020001800005225415412483274200020002000541541111001100007311611538100010001000542542542542542
200454140432530001000200020001800005225415412483274200020002000541541111001100007311611538100010001000542542542542542

Test 2: Latency 1->2 roundtrip

Code:

  fcvtmu w0, h0
  fmov d0, x0
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 13.0038

retire uop (01)cycle (02)0318191e1f3f4f51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)6061696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int store (96)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cfd0d5map dispatch bubble (d6)dbddfetch restart (de)e0? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
302041300381008000013002311941725401001010020000100001002000010000500621497914801034101300141300381300381254763126246301002001000020000200100002000013003813003811202011009910001010010000100100000000001310121603212952510000100001000010100130039130039130039130039130039
302041300381008000013002311941725401001010020000100001002000010000500621497914801034101300581300401300381254763126248301002001000020000200100002000013003813003811202011009910001010010000100100000000001310121602212952510000100001000010100130039130039130039130039130045
302041300401008007013002311941725401001010020000100001002000010000500621497914801034101300771300381300381254763126246301002001000020000200100002000013003813003811202011009910001010010000100100000000001310121602212952510000100001000010100130039130039130039130039130039
302041300381008000013002311941725401001010020000100001002000010000500621497914801034101300951300381300381254763126246301002001000020000200100002000013003813003811202011009910001010010000100100000000001310121602212952510000100001000010100130039130039130039130039130039
3020413003810080000130023119417254010010100200001000010020000100005006214979148010341013005813003813004112547614126246301002001000020000200100002000013003813003811202011009910001010010000100100000000001310121602212952510000100001000010100130039130039130040130039130039
302041300381008000013002311941725401001010020000100001082000010000500621497914801034101300721300381300381254763126246301002001000020000200100002000013003813003811202011009910001010010000100100000000001310121602212952510000100001000010100130039130039130039130039130039
302041300381008000013002311941825401001010020000100001002000010000500621497914801034101303011300381300381254763126314301002001000020000200100002000013003813003811202011009910001010010000100100000000001310121602212952510000100001000010100130039130039130039130040130039
302041300381008000013002311941725401001010020000100001002000010000500621497914801034101300691300381300381254763126246301002001000020000200100002000013003813003811202011009910001010010000100100000000001310121602212952510000100001000010100130039130039130039130039130039
302041300381008000013002311941725401001010020000100001002000010000500621497914801034101300931300381300381254763126246301002001000020000200100002000013003813003811202011009910001010010000100100000000001310121602212952510000100001000010100130039130039130039130039130039
302041300381008000013002311941725401001010020000100001002000010000500621497914801034101301241300381300381254763126246301002001000020000200100002000013003813003811202011009910001010010000100100000000001310121602212952510000100001000010100130039130039130039130039130040

1000 unrolls and 10 iterations

Result (median cycles for code): 13.0038

retire uop (01)cycle (02)03l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e3a3f4f51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acafbranch mispred nonspec (cb)cdcfd2d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
30024130038100801000013002411941725400101001120000100001020000100005062149791480002511300131300391300381255263126320300102010060200002010000200001300381300381120021109101001010000100100000300000127001241112952510001100001000010010130121130039130039130039130039
300241300381008000000130023119417254001010010200001000010200001000050621497914800025113001313003813003812549816126262300102010000200002010000200001300381300381120021109101001010000100100000000000127001161212952510000100001000010010130080130042130039130039130058
3002413003897400000013002311941725400101001020000100001020000100005562149791480002511300131300381300411255473126269300102010000200002010000201231300421300381120021109101001010000100100000000000127001161112952510000100001000010010130039130039130039130039130039
3002413003897400000013002311941725400101001020000100001020000100005062149791480002511300131300381300381254983126286301822010000200002010000200001300381300381120021109101001010000100100000000001127001161112952510000100001000010010130039130039130039130039130039
3002413003897400000013011411941749400101001020000100001020000100005062149791480002501300131300381300381254983126268300102010000200002010000200001301221300381120021109101001010000100100000000000127001241112952510000100001000010010130039130039130039130039130086
3002413003899401000013002311941725400101001020000100001020000100005062149791480002511300131300381300381254989126269300102010062200002010000200001300381300381120021109101001010000100100000000000127002161112952510000100001000010010130048130040130119130039130039
3002413003897400003013002311941725400171001020000100001020000100005062149791480002511300131300381300381254983126308300102010000200002010000200001300381300381120021109101001010000100100000003000127001161112952510000100001000010010130039130039130039130039130039
3002413003897400010013002311941725400101001020000100001020000100005062149791480002501300131300381300381254983126333300102010000200002010000200001300391300401120021109101001010000100100000000000127001251112952510000100001000010010130043130121130039130039130039
3002413003897400000013002311941725400101001120000100001020000100495062149791480002511300131300381300381254983126268300102010000200002010000200001300381300381120021109101001010000100100000300000127001161112952510000100001000010010130039130069130039130039130039
3002413003897410003013002311941767400361001420012100001020000100005062150271480069501303491300381300381254983126297300102010000200002010000200001300381300381120021109101001010000100100000000000127001161112952510000100001000010010130039130039130039130039130039

Test 3: throughput

Count: 8

Code:

  fcvtmu w0, h8
  fcvtmu w1, h8
  fcvtmu w2, h8
  fcvtmu w3, h8
  fcvtmu w4, h8
  fcvtmu w5, h8
  fcvtmu w6, h8
  fcvtmu w7, h8
  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fld unit uop (a6)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)dde0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
160204400623220322524010480100160004100160020500144013204002240041400411997761999216012020016003220016003240041400411180201100991008010010000011151171160400388000080000801004004240042400424004240042
160204400413100322524010480100160004100160020500144013204002240041400411997761999216012020016003220016003240041400411180201100991008010010000011151170160400388000080000801004004240042400424004240042
160204400413100322524010480100160004100160020500144013204002240041400411997761999216012020016003220016003240041400411180201100991008010010000011151170160400388000080000801004004240042400424004240042
160204400413110602524010480100160004100160020500144013204002240041400411997761999216012020016024020016003240041400411180201100991008010010000133011151170160400388000080000801004004240042400424004240042
1602044004131006972524010480100160004100160020500144013204002240041400411997761999216012020016003220016003240041400411180201100991008010010000011151170160400388000080000801004004240042400424004240042
1602044004131012322524010480100160004100160020500144013204002240041400411997761999216012020016003220016003240041400411180201100991008010010000011151170161400388000080000801004004240042400424004240042
160204400413110322524010480100160004100160020500144013214002240041400411997761999216012020016003220016003240041400411180201100991008010010000011151170160400388000080000801004004240042400424004240042
160204400413100322524010480100160004100160020500144013214002240041400411997761999216012020016003220016003240041400411180201100991008010010000011151170160400388000080000801004004240042400424004240042
160204400413100322524010480100160004100160020500144013214002240041400411997761999216012020016003220016003240041400411180201100991008010010000011151170160400388000080000801004004240042400424004240042
160204400413100322524010480100160004100160020500144013214002240041400411997761999216012020016003220016003240041400411180201100991008010010000011151170160400388000080000801004004240042400424004240042

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

retire uop (01)cycle (02)03mmu table walk instruction (07)1e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
16002440055310000422524001080010160000101600005014400004002240041400411999632002116001020160000201600004004140041118002110910800101000035020916712400388000080000800104004240042400424004240042
16002440041310000422524001080010160000101600005014400004002240041400411999632002116001020160000201600004004140041118002110910800101000005020816116400388000080000800104004240042400424004240042
160024400413110006122524001080010160000101600005014400004002240041400411999632002116001020160000201600004004140041118002110910800101020005020516127400388000080000800104004240042400424004240042
160024400413100004225240010800101600001016000050144000040022400414004119996320021160010201600002016000040041400411180021109108001010000050207161110400388000080000800104004240042400424004240042
1600244004131000070252400108001016000010160000501440000400224004140041199963200211600102016000020160236400414004111800211091080010100000502051645400388000080000800104004240042400424004240042
1600244004131000042252400108001016000010160000501440000400224004140041199963200211600102016025020160000400414004111800211091080010100000502061666400388000080000800104004240042400424004240042
16002440041310000707252400108001016000010160000501440000400224004140041199963200211600102016000020160000400414004111800211091080010100010502051665400388000080000800104004240042400424004240042
16002440041311000422524001080010160000101600005014400004002240041400411999632002116001020160000201600004004140041118002110910800101000005020616105400388000080000800104004240042400424004240042
1600244004131000042252400108001016000010160000501440000400224004140041199963200211600102016000020160000400414004111800211091080010100000502051665400388000080000800104004240042400424004240042
1600244004131100042252400108001016000010160000501440000400224004140041199963200211600102016000020160000400414004111800211091080010100000502041669400388000080000800104004240042400424004240042