Apple M1 Microarchitecture Research by Dougall Johnson

Firestorm: Overview | Base Instructions | SIMD and FP Instructions
Icestorm:  Overview | Base Instructions | SIMD and FP Instructions

FCVTMU (scalar, H to X)

Test 1: uops

Code:

  fcvtmu x0, h0
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 3.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 2.000

retire (01)cycle (02)0307090b1e1f3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch fp/simd (57)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op fp/simd (7e)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst integer (97)a6a8accfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
200454140000043253000100020002000180001522541541248327420002000200054154111100110000007311611538100010001000542542542542542
200454140000043253000100020002000180000522541541248327420002000200054154111100110000007311622538100010001000542542542542542
200454140000043253000100020002000180000522541541248327420002000200054154111100110000007311611538100010001000542542542542542
200454140000043253000100020002000180001522541541248327420002000200054154111100110000007311611538100010001000542542542542542
200454140000043253000100020002000180001522541541248327420002000200054154111100110000007321611538100010001000542542542542542
200454140000043253000100020002000180000522541541248327420002000200054154111100110000007311611538100010001000542542542542542
200454140000043253000100020002000180001522541541248327420002000200054154111100110000007311611538100010001000542542542542542
200454140000043253000100020002000180001522541541248327420002000200054154111100110000007511611538100010001000542542542542542
200454140000043253000100020002000180001522541541248327420002000200054154111100110000007511611538100010001000542542542542542
200454140000043253000100020002000180001522541541248327420002000200054154111100110000007311611538100010001000542542542542542

Test 2: Latency 1->2 roundtrip

Code:

  fcvtmu x0, h0
  fmov d0, x0
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 13.0038

retire (01)cycle (02)030818191e1f3f4f51inst issue (52)~issue int (53)~issue fp/simd (54)~issue ld/st (55)~dispatch int (56)~dispatch fp/simd (57)~dispatch ld/st (58)huge thing int (59)huge thing ld/st (5a)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op ld/st (7d)~map op fp/simd (7e)~map lookup int (7f)~map lookup ld/st (80)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa0a6a8acbranch mispredict (cb)cfd0d5d6dbddinst fetch restart (de)e0? int output thing (e9)ebld/st retires (ed)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
3020413003810080000013002311941725401001010020000100001002000010000500621497914801034113004413003813003812549331263063010020010000200002001000020000130038130038112020110099100101001000010001000000013101216022129525100000100001000010100130039130039130039130039130039
3020413003810080000013002311941725401001010020000100001002000010000500621497914801034013001313003813003812547631262783010020010000200002001000020000130038130038112020110099100101001000010001000000013101216022129525100000100001000010100130039130039130039130039130039
3020413006897400072013002311941725401001010020000100001002000010000500621497914801034013001313003813003812547631262473010020010000200002001000020000130038130038112020110099100101001000010001000000013101216022129525100000100001000010100130039130039130039130039130067
302041300389740000013002311941725401001010020000100001002000010000500621497914801034013001313003813003812547631262513010020010000200002001000020128130038130038112020110099100101001000010001000000013101216032129525100000100001000010100130039130039130039130042130039
302041300389740000013002311941725401001010020000100001002000010000500621497914801034013001313003813003812547631262483010020010000200002001000020000130038130038112020110099100101001000010001000000013101217022129525100000100001000010100130039130039130039130039130039
302041300389740000013002311941725401001010020000100001002000010000500621497914801034113001313003813003812547731262463010020010000200002001000020000130038130038112020110099100101001000010001000000013101216022129525100000100001000010100130039130039130039130039130039
302041300389740000013002311941725401001010020000100001002000010000500621497914801034113001313003813003812547631262463010020010000200002001000020000130038130038112020110099100101001000010001000000013101217122129525100000100001000010100130039130039130039130039130039
302041300389740001287013002311941725401001010020000100001002000010000551621521914801034013001313003813003812547631262463010020010000200002001000020000130038130038112020110099100101001000010001000000013101216022129525100000100001000010100130039130039130039130039130039
30204130038974000828013002311941725401001010020000100001002000010000500621497914801034013001313003813003812547631262463010020010000200002001000020000130038130038112020110099100101001000010001000000013101216022129525100000100001000010100130039130039130039130039130039
3020413003897400069013002311941725401001010020000100001002000010000500621497914801034013001313003813003812547631262463010020010000200002001000020000130038130038112020110099100101001000010001000000013101216022129525100000100001000010100130039130039130039130039130039

1000 unrolls and 10 iterations

Result (median cycles for code): 13.0038

retire (01)cycle (02)03070b181e1f3f4f51inst issue (52)~issue int (53)~issue fp/simd (54)~issue ld/st (55)~dispatch int (56)~dispatch fp/simd (57)~dispatch ld/st (58)huge thing int (59)huge thing ld/st (5a)huge thing fp/simd (5b)60696b6d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op ld/st (7d)~map op fp/simd (7e)~map lookup int (7f)~map lookup ld/st (80)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa6a8accdcfd5d6ddinst fetch restart (de)e0? int output thing (e9)ld/st retires (ed)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
3002413003897400000130023119417254001010010200001000010200001000050621497914800025113001301300381300991255003126268300102010000200002010000200001300381300381120021109101001010000101000000012701161112952510000100001000010010130039130039130039130039130039
3002413003897400000130023119417254001010010200001000010200001000050621497914800025113001301300411300381254983126268300102010000200002010000200001300381300381120021109101001010000101000000012701161112952510000100001000010010130039130039130039130039130039
3002413003897400000130023119417254001010010200001000010200001000050621497914800025113001301300381300381254983126268300102010000200002010000200001300381300381120021109101001010000101000000012701161212952710000100001000010010130039130039130039130039130039
30024130038973000001300231194172540010100102000310000102000010000506214979148000251130013013003813003912549831262683001020100002000020100002000013003813003811200211091010010100001010000221012701161112952510000100001000010010130039130039130039130039130039
3002413003897400000130023119417254001010010200001000010200001000050621497914800025113001301300381300381254983126268300102010000200002010000200001300381300381120021109101001010000101000000012701161112952510000100001000010010130039130079130042130039130040
3002413003897400000130023119420254001010010200001000010200001000050621497914800025113001301300381300381254983126268300102010000200002010000200001300381300381120021109101001010000101000000012701161112952510000100001000010010130039130039130039130039130039
3002413003897400000130023119417254001010010200001000110200001000050621497914800025113001301300381300381254983126268300102010000200002010000200001300381300381120021109101001010000101000000012701161112952510000100001000010010130039130039130039130039130039
3002413003897400000130023119417254001010010200001000010200001000050621497914800025113001301300381300381254983126268300102010000200002010000200001300381300381120021109101001010000101000000012701161112952510000100001000010010130039130039130039130039130048
30024130039974000792340130023119417474001010010200001000010200001000050621497914833658113033801303691301201254983126268300102010000200002010122200001300381300383120021109101001010000101000009750012702161212952510000100001000010010130039130039130039130039130039
3002413003897400060130023119417254001010010200001000010200001000050621497914800025113007401300381300381254983126268300102010000200002010000200001300381300381120021109101001010000101000000012701161112952510000100001000010010130039130039130039130039130039

Test 3: throughput

Count: 8

Code:

  fcvtmu x0, h8
  fcvtmu x1, h8
  fcvtmu x2, h8
  fcvtmu x3, h8
  fcvtmu x4, h8
  fcvtmu x5, h8
  fcvtmu x6, h8
  fcvtmu x7, h8
  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

retire (01)cycle (02)031e3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696b6d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)9fa8acc5branch mispredict (cb)cdcfd6dde0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
160204400623110222252401048010016000410016002050014401321400220400414004119977619992160120200160032200160032400414004111802011009910080100100001115117160400388000080000801004004240042400424004240042
16020440041311032252401048010016000410016002050014401321400220400414004119977619992160120200160032200160032400414004111802011009910080100100001115117160400388000080000801004004240042400424004240042
16020440041310032252401048010016000410016002050014401321400220400414004119977619992160120200160032200160032400414004111802011009910080100100001115117160400388000080000801004004240042400424004240042
160204400413111274252401048010016000410016002050014401320400220400414004119977619992160120200160032200160032400414004111802011009910080100100001115117160400388000080000801004004240042400424004240042
16020440041310032252401048010016000410016002050014420490400223400414004119977619992160120200160032200160032400414004111802011009910080100100001115117160400388000080000801004004240042400424004240042
160204400413220975252401048010016000410016002050014401320400220400414004119977619992160120200160032200160032400414004111802011009910080100100001115117160400388000080000801004004240042400424004240042
16020440041310032252401048010016000410016002050014401321400220400414004119977619992160120200160032200160032400414004111802011009910080100100001115117160400388000080000801004004240042401864004240042
160204400413100549252401048010016000410016002050014401321400220400414004119977619992160120200160032200160032400414004111802011009910080100100001115117160400388000080000801004004240042400424004240042
16020440041311332252401048010016000410016002050014401321400220400414004119977619992160120200160032200160032400414004111802011009910080100100001115117161400388000080000801004004240042400424004240042
16020440041311032252401048010016000410016002050014401321400220400414004119977619992160120200160032200160032401264004111802011009910080100100001115117160400388000080000801004004240042400424004240042

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

retire (01)cycle (02)030818191e1f3a3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)6061696d6edispatch stall (70)74scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)9fa0a1a6a8a9abacc2cfd0d2itlb miss (d4)d5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
16002440042310000000422524001080010160000101600005014400000040022400414004119996032002116001020160000201600004004140041118002110910800101000000000502000041644400388000080000800104004240042400424004240042
16002440041310000000422524001080010160000101600005014400000040022400414004119996032002116001020160000201600004004140041118002110910800101000000000502000041644400388000080000800104004240042400424004240042
16002440041310000000792524001080010160000101600005014400000040022400414004119996032002116001020160000201600004004140041118002110910800101000300000502000041643400388000080000800104004240042400424004240042
16002440041311001000422524001080010160000101600005014400000040022400414004119996532002116001020160000201600004004140041118002110910800101000000000502000041643402988000080000800104004240042400424004240042
16002440041311000000422524001080010160000101600005014400000040022400414004119996032002116001020160000201600004004140041118002110910800101002000030502000041644400388000080000800104004240042400424004240042
1600244004131000000021327824342781162162138101616285014616540040787408944100620274093205571623962016259420161788410604091113180021109108001010000120741005220000313344408238112780000800104059741070411474108341306
16002441054317100000193820624176880816161176101609845014507520040344404244028320164041202831608262016143622161040403624067871800211091080010102021001868051710010057047410728154480000800104155641453413874146541075
160024412303341121628621672282484824001080010160000101600005014400000041410411544004119996010820428162680201630942016287441297411471618002110910800101020010012282502150049834401068000080000800104004240042400424004240042
16002440041321000000842524001080010160000101600005014400001040022400414004119996032002116001020160000201600004004140041118002110910800101000000000502000041634400388000080000800104004240042400424004240042
16002440041310000000422524001080010160000101600005014400001040022400414004120017032002116001020160000201600004004140041118002110910800101000000000502000031644400388000080000800104004240042400424004240042