Firestorm: FCVTMU (scalar, H to X) measurements

Code:

  fcvtmu x0, h0

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 3.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 2.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	09	l2 tlb miss data (0b)	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
2004	541	4	0	0	0	0	0	43	25	3000	1000	2000	2000	18000	1	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	0	73	1	16	1	1	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	0	0	0	0	43	25	3000	1000	2000	2000	18000	0	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	0	73	1	16	2	2	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	0	0	0	0	43	25	3000	1000	2000	2000	18000	0	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	0	73	1	16	1	1	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	0	0	0	0	43	25	3000	1000	2000	2000	18000	1	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	0	73	1	16	1	1	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	0	0	0	0	43	25	3000	1000	2000	2000	18000	1	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	0	73	2	16	1	1	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	0	0	0	0	43	25	3000	1000	2000	2000	18000	0	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	0	73	1	16	1	1	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	0	0	0	0	43	25	3000	1000	2000	2000	18000	1	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	0	73	1	16	1	1	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	0	0	0	0	43	25	3000	1000	2000	2000	18000	1	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	0	75	1	16	1	1	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	0	0	0	0	43	25	3000	1000	2000	2000	18000	1	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	0	75	1	16	1	1	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	0	0	0	0	43	25	3000	1000	2000	2000	18000	1	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	0	73	1	16	1	1	538	1000	1000	1000	542	542	542	542	542

Test 2: Latency 1->2 roundtrip

Code:

  fcvtmu x0, h0
  fmov d0, x0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 13.0038

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	18	19	1e	1f	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	ac	branch mispred nonspec (cb)	cf	d0	d5	map dispatch bubble (d6)	db	dd	fetch restart (de)	e0	? int output thing (e9)	eb	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30204	130038	1008	0	0	0	0	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	1	130044	130038	130038	125493	3	126306	30100	200	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	1310	1	2	16	0	2	2	129525	10000	0	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	1008	0	0	0	0	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	0	130013	130038	130038	125476	3	126278	30100	200	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	1310	1	2	16	0	2	2	129525	10000	0	10000	10000	10100	130039	130039	130039	130039	130039
30204	130068	974	0	0	0	72	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	0	130013	130038	130038	125476	3	126247	30100	200	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	1310	1	2	16	0	2	2	129525	10000	0	10000	10000	10100	130039	130039	130039	130039	130067
30204	130038	974	0	0	0	0	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	0	130013	130038	130038	125476	3	126251	30100	200	10000	20000	200	10000	20128	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	1310	1	2	16	0	3	2	129525	10000	0	10000	10000	10100	130039	130039	130039	130042	130039
30204	130038	974	0	0	0	0	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	0	130013	130038	130038	125476	3	126248	30100	200	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	1310	1	2	17	0	2	2	129525	10000	0	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	974	0	0	0	0	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	1	130013	130038	130038	125477	3	126246	30100	200	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	1310	1	2	16	0	2	2	129525	10000	0	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	974	0	0	0	0	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	1	130013	130038	130038	125476	3	126246	30100	200	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	1310	1	2	17	1	2	2	129525	10000	0	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	974	0	0	0	1287	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	551	6215219	14801034	0	130013	130038	130038	125476	3	126246	30100	200	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	1310	1	2	16	0	2	2	129525	10000	0	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	974	0	0	0	828	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	0	130013	130038	130038	125476	3	126246	30100	200	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	1310	1	2	16	0	2	2	129525	10000	0	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	974	0	0	0	69	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	0	130013	130038	130038	125476	3	126246	30100	200	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	1310	1	2	16	0	2	2	129525	10000	0	10000	10000	10100	130039	130039	130039	130039	130039

1000 unrolls and 10 iterations

Result (median cycles for code): 13.0038

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss data (0b)	18	1e	1f	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30024	130038	974	0	0	0	0	0	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	1	130013	0	130038	130099	125500	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	10000	0	0	0	1270	1	16	1	1	129525	10000	10000	10000	10010	130039	130039	130039	130039	130039
30024	130038	974	0	0	0	0	0	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	1	130013	0	130041	130038	125498	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	10000	0	0	0	1270	1	16	1	1	129525	10000	10000	10000	10010	130039	130039	130039	130039	130039
30024	130038	974	0	0	0	0	0	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	1	130013	0	130038	130038	125498	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	10000	0	0	0	1270	1	16	1	2	129527	10000	10000	10000	10010	130039	130039	130039	130039	130039
30024	130038	973	0	0	0	0	0	130023	119417	25	40010	10010	20003	10000	10	20000	10000	50	6214979	14800025	1	130013	0	130038	130039	125498	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	10000	2	21	0	1270	1	16	1	1	129525	10000	10000	10000	10010	130039	130039	130039	130039	130039
30024	130038	974	0	0	0	0	0	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	1	130013	0	130038	130038	125498	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	10000	0	0	0	1270	1	16	1	1	129525	10000	10000	10000	10010	130039	130079	130042	130039	130040
30024	130038	974	0	0	0	0	0	130023	119420	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	1	130013	0	130038	130038	125498	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	10000	0	0	0	1270	1	16	1	1	129525	10000	10000	10000	10010	130039	130039	130039	130039	130039
30024	130038	974	0	0	0	0	0	130023	119417	25	40010	10010	20000	10001	10	20000	10000	50	6214979	14800025	1	130013	0	130038	130038	125498	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	10000	0	0	0	1270	1	16	1	1	129525	10000	10000	10000	10010	130039	130039	130039	130039	130039
30024	130038	974	0	0	0	0	0	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	1	130013	0	130038	130038	125498	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	10000	0	0	0	1270	1	16	1	1	129525	10000	10000	10000	10010	130039	130039	130039	130039	130048
30024	130039	974	0	0	0	792	340	130023	119417	47	40010	10010	20000	10000	10	20000	10000	50	6214979	14833658	1	130338	0	130369	130120	125498	3	126268	30010	20	10000	20000	20	10122	20000	130038	130038	3	1	20021	10	9	10	10010	10000	10	10000	0	9750	0	1270	2	16	1	2	129525	10000	10000	10000	10010	130039	130039	130039	130039	130039
30024	130038	974	0	0	0	6	0	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	1	130074	0	130038	130038	125498	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	10000	0	0	0	1270	1	16	1	1	129525	10000	10000	10000	10010	130039	130039	130039	130039	130039

Test 3: throughput

Count: 8

Code:

  fcvtmu x0, h8
  fcvtmu x1, h8
  fcvtmu x2, h8
  fcvtmu x3, h8
  fcvtmu x4, h8
  fcvtmu x5, h8
  fcvtmu x6, h8
  fcvtmu x7, h8

Initialization

  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	map dispatch bubble (d6)	dd	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	40062	311	0	222	25	240104	80100	160004	100	160020	500	1440132	1	40022	0	40041	40041	19977	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	1	1	1	5117	16	0	40038	80000	80000	80100	40042	40042	40042	40042	40042
160204	40041	311	0	32	25	240104	80100	160004	100	160020	500	1440132	1	40022	0	40041	40041	19977	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	1	1	1	5117	16	0	40038	80000	80000	80100	40042	40042	40042	40042	40042
160204	40041	310	0	32	25	240104	80100	160004	100	160020	500	1440132	1	40022	0	40041	40041	19977	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	1	1	1	5117	16	0	40038	80000	80000	80100	40042	40042	40042	40042	40042
160204	40041	311	12	74	25	240104	80100	160004	100	160020	500	1440132	0	40022	0	40041	40041	19977	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	1	1	1	5117	16	0	40038	80000	80000	80100	40042	40042	40042	40042	40042
160204	40041	310	0	32	25	240104	80100	160004	100	160020	500	1442049	0	40022	3	40041	40041	19977	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	1	1	1	5117	16	0	40038	80000	80000	80100	40042	40042	40042	40042	40042
160204	40041	322	0	975	25	240104	80100	160004	100	160020	500	1440132	0	40022	0	40041	40041	19977	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	1	1	1	5117	16	0	40038	80000	80000	80100	40042	40042	40042	40042	40042
160204	40041	310	0	32	25	240104	80100	160004	100	160020	500	1440132	1	40022	0	40041	40041	19977	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	1	1	1	5117	16	0	40038	80000	80000	80100	40042	40042	40186	40042	40042
160204	40041	310	0	549	25	240104	80100	160004	100	160020	500	1440132	1	40022	0	40041	40041	19977	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	1	1	1	5117	16	0	40038	80000	80000	80100	40042	40042	40042	40042	40042
160204	40041	311	3	32	25	240104	80100	160004	100	160020	500	1440132	1	40022	0	40041	40041	19977	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	1	1	1	5117	16	1	40038	80000	80000	80100	40042	40042	40042	40042	40042
160204	40041	311	0	32	25	240104	80100	160004	100	160020	500	1440132	1	40022	0	40041	40041	19977	6	19992	160120	200	160032	200	160032	40126	40041	1	1	80201	100	99	100	80100	100	0	0	1	1	1	5117	16	0	40038	80000	80000	80100	40042	40042	40042	40042	40042

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	61	69	6d	6e	map stall dispatch (70)	rob full (74)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ab	ac	c2	cf	d0	d2	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	40042	310	0	0	0	0	0	0	42	25	240010	80010	160000	10	160000	50	1440000	0	0	40022	40041	40041	19996	0	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	0	0	5020	0	0	0	4	16	4	4	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	310	0	0	0	0	0	0	42	25	240010	80010	160000	10	160000	50	1440000	0	0	40022	40041	40041	19996	0	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	0	0	5020	0	0	0	4	16	4	4	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	310	0	0	0	0	0	0	79	25	240010	80010	160000	10	160000	50	1440000	0	0	40022	40041	40041	19996	0	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	3	0	0	0	0	0	5020	0	0	0	4	16	4	3	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	311	0	0	1	0	0	0	42	25	240010	80010	160000	10	160000	50	1440000	0	0	40022	40041	40041	19996	5	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	0	0	5020	0	0	0	4	16	4	3	40298	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	311	0	0	0	0	0	0	42	25	240010	80010	160000	10	160000	50	1440000	0	0	40022	40041	40041	19996	0	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	2	0	0	0	0	3	0	5020	0	0	0	4	16	4	4	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	310	0	0	0	0	0	0	213	278	243427	81162	162138	10	161628	50	1461654	0	0	40787	40894	41006	20274	0	93	20557	162396	20	162594	20	161788	41060	40911	13	1	80021	10	9	10	80010	10	0	0	0	1	2	0	7410	0	5220	0	0	0	3	133	4	4	40823	81127	80000	80010	40597	41070	41147	41083	41306
160024	41054	317	1	0	0	0	0	0	1938	206	241768	80816	161176	10	160984	50	1450752	0	0	40344	40424	40283	20164	0	41	20283	160826	20	161436	22	161040	40362	40678	7	1	80021	10	9	10	80010	10	2	0	2	1	0	0	1868	0	5171	0	0	100	5	70	4	7	41072	81544	80000	80010	41556	41453	41387	41465	41075
160024	41230	334	1	12	16	2862	1672	2	8248	48	240010	80010	160000	10	160000	50	1440000	0	0	41410	41154	40041	19996	0	108	20428	162680	20	163094	20	162874	41297	41147	16	1	80021	10	9	10	80010	10	2	0	0	1	0	0	1228	2	5021	5	0	0	4	98	3	4	40106	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	321	0	0	0	0	0	0	84	25	240010	80010	160000	10	160000	50	1440000	1	0	40022	40041	40041	19996	0	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	0	0	5020	0	0	0	4	16	3	4	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	310	0	0	0	0	0	0	42	25	240010	80010	160000	10	160000	50	1440000	1	0	40022	40041	40041	20017	0	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	0	0	5020	0	0	0	3	16	4	4	40038	80000	80000	80010	40042	40042	40042	40042	40042

FCVTMU (scalar, H to X)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations