Apple M1 Microarchitecture Research by Dougall Johnson

Firestorm: Overview | Base Instructions | SIMD and FP Instructions
Icestorm:  Overview | Base Instructions | SIMD and FP Instructions

FCVTMU (scalar, S to W)

Test 1: uops

Code:

  fcvtmu w0, s0
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 3.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 2.000

retire (01)cycle (02)03181e1f3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch fp/simd (57)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op fp/simd (7e)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst integer (97)a6a8a9accfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
20045414000432530001000200020001800015225415412483274200020002000541541111001100000007321622538100010001000542542542542542
20045414000432530001000200020001800015225415412483274200020002000541541111001100000007321622538100010001000542542623542542
20045414000432530001000200020001800015225415412483274200020002000541541111001100000007321622538100010001000542542542542542
20045414000432530001000200020001800015225415412483274200020002000541541111001100000007321622538100010001000542542542542542
20045414000432530001000200020001800015225415412483274200020002000541541111001100000007321622538100010001000542542542542542
20045414000432530001000200020001800015225415412483274200020002000541541111001100000007321622538100010001000542542542542542
20045414000432530001000200020001800015225415412483274200020002000541541111001100000007321622538100010001000542542542542542
20045414000432530001000200020001800015225415412483274200020002000541541111001100000007321622538100010001000542542542542542
20045414060432530001000200020001800015225415412483274200020002000541541111001100000007321622538100010001000542542542542542
20045414030432530001000200020001800015225415412483274200020002000541541111001100000007321622538100010001000542542542542542

Test 2: Latency 1->2 roundtrip

Code:

  fcvtmu w0, s0
  fmov d0, x0
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 13.0038

retire (01)cycle (02)03080b18191e1f3a3f4f51inst issue (52)~issue int (53)~issue fp/simd (54)~issue ld/st (55)~dispatch int (56)~dispatch fp/simd (57)~dispatch ld/st (58)huge thing int (59)huge thing ld/st (5a)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op ld/st (7d)~map op fp/simd (7e)~map lookup int (7f)~map lookup ld/st (80)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa0a1a6a7a8a9acc2c5branch mispredict (cb)cdcfd0d5d6ddinst fetch restart (de)e0? int output thing (e9)ld/st retires (ed)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
302041300439740000000130046119417254010010100200001000010020000100005006214979148010341130013130038130038125483612624230100200100022000620010002200061300381300381120201100991001010010000100001000000000111131701161112953410000100001000010100130039130039130039130039130039
302041300389740000000130033119417254010010100200001000010020000100005006214979148010340130013130038130038125483612624130100200100022000620010002200061300381300381120201100991001010010000100001000000000111131701161112953310000100001000010100130039130039130039130039130039
302041300389740000000130037119417254010010100200001000010020000100005006214979148010340130013130038130038125476312624630100200100002000020010000200001300381300381120201100991001010010000100001000000000000131012162212952510021100001000010100130039130039130039130039130039
302041300389740000000130047119417254010010100200001000010020000100005006214979148010340130013130038130038125476312624630100200100002000020010000200001300381300381120201100991001010010000100001000000000000131012162112952810000100001000010100130039130039130039130075130074
302041300389750000105600130027119417254010010100200001000010020000100005006214979148010341130013130038130038125476312624630100200100002000020010000200001300381300381120201100991001010010000100001000000000000131012163212952510000100001000010100130039130039130039130039130039
302041300459740000000130023119417254010010100200001000010020000100005006215444148010340130013130038130038125476312624630100200100002000020010000200001300381300381120201100991001010010000100001000000000000131012162212952510000100001000010100130039130039130039130039130039
302041300389740000000130023119417254010010100200001000010020000100005006214979148010341130013130038130038125476312624630100200100002000020010000200001300381300381120201100991001010010000100001000000000000131012162212952510000100001000010100130039130039130039130039130039
3020413003897400000001300681194172540100101002000010000100200001000050062149791480103401300131300381300381254763126246301002001000020000200100002000013003813003811202011009910010100100001000010000000020001705162223413134310060100001000010100132113132340132342132264132419
3020413227599111282350553080113157312005346940260101702006710043132210451044150062327921480103411311341305521319941265581851278863559225211896244902381263425228132871132856411202011009910010100100001004410062000340001855061862212952510000100001000010100130039130039130039130039130039
302041300389740000000130023119417254010010100200001000010020000100005006214979148010341130013130038130038125476312624630100200100002000020010000200001300381300381120201100991001010010000100001000000000000131012162212952510000100001000010100130039130039130039130039130039

1000 unrolls and 10 iterations

Result (median cycles for code): 13.0038

retire (01)cycle (02)0307080918191e1f3a3f4f51inst issue (52)~issue int (53)~issue fp/simd (54)~issue ld/st (55)~dispatch int (56)~dispatch fp/simd (57)~dispatch ld/st (58)huge thing int (59)huge thing ld/st (5a)huge thing fp/simd (5b)60696b6d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op ld/st (7d)~map op fp/simd (7e)~map lookup int (7f)~map lookup ld/st (80)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa6a8acc5branch mispredict (cb)cfd5d6ddinst fetch restart (de)e0? int output thing (e9)ebld/st retires (ed)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
3002413004010080000000013002311941725400101001020000100001020000100005062149791480002511300130130038130041125498312626830010201000020000201006320000130038130038112002110910100101000010100000000127021611129525100000100001000010010130039130039130039130039130039
3002413003810082000000013002411941725400101001020000100001020000100005062149791480002501300130130038130038125498312626830010201000020000201000020000130038130038112002110910100101000010100000000127011611129525100000100001000010010130039130039130039130039130039
3002413004110070000000013002311941725400101001020000100001020000100005062149791480002501300130130038130038125498312626830010201000020000201000020000130038130038112002110910100101000010100000000127011611129525100000100001000010010130039130039130039130039130039
3002413003810080000000013002311941725400101001020000100001020000100005062149791480002501300130130038130038125498312626830010201000020000201000020000130038130038112002110910100101000010100000000127011611129525100000100001000010010130039130039130039130039130039
3002413003810080000000013002311941725400101001020000100001020000100005062149791480002511300130130038130038125498312626830010201000020000201000020000130038130038112002210910100101000010100000000127011621129525100000100001000010010130039130039130039130039130039
30024130038100800000000130023119414254001010010200001000010200001000050621497914800025113001301300401300431254983126268300102010000200002010000200001300381300381120021109101001010000101000063000127011611129525100000100001000010010130039130039130039130039130039
3002413003810080100000013002311942025400101001020000100001020000100005062149791480002511300130130038130038125498312626830010201000020000201000020000130038130038112002110910100101000010100000010127011611129552100000100001000010010130039130039130039130039130039
3002413003810080000000013002311941725400101001020000100001020000100005062149791480002511300130130038130038125498312626830010201000020000201000020131130082130040112002110910100101000010100000000127011611129525100000100001000010010130039130039130039130039130039
300241300389740000000013002311941725400101001020000100001020000100005062149791480002511300160130038130038125498312626830010201000020000201000020000130038130038112002110910100101000010100000000127011611129525100000100001000010010130039130039130039130039130039
300241300389740000000013002311941725400101001020000100001020000100005062149791480002511300130130038130038125498312626830010201000020000201000020000130038130038112002110910100101000010100000000127011611129529100000100001000010010130039130039130039130039130039

Test 3: throughput

Count: 8

Code:

  fcvtmu w0, s8
  fcvtmu w1, s8
  fcvtmu w2, s8
  fcvtmu w3, s8
  fcvtmu w4, s8
  fcvtmu w5, s8
  fcvtmu w6, s8
  fcvtmu w7, s8
  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

retire (01)cycle (02)031e3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)9fa8a9acc5branch mispredict (cb)cdcfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
1602044004129903225240104801001600041001600205001440132140022400414004119977619992160120200160032200160032400414004111802011009910080100100000111511701600400388000080000801004004240042400424004240042
16020440041299022225240104801001600041001600205001440132140022400414004119977619992160120200160032200160456400414004111802011009910080100100000111511701600400388000080000801004004240042400424004240042
1602044004129903225240104801001600041001600205001440132040108400414004119977619992160120200160032200160032400414004111802011009910080100100000111511701600400388000080000801004004240042400424004240042
1602044004129907425240104801001600041001600205001440132040022400414004119977619992160120200160032200160032400414004111802011009910080100100000111511701600400388000080000801004004240042400424004240042
1602044004130003225240104801001600041001600205001440132040022400414004119977619992160120200160032200160032400414004111802011009910080100100000111511701600400388000080000801004004240042400424004240042
16020440041300035925240104801001600041001600205001440132140022401964020419977619992160120200160032200160248401214004111802011009910080100100000111511704310401738000080000801004004240042400424004240042
1602044004130007425240104801001600041001600205001440132140022400414004119977619992160120200160032200160032400414004111802011009910080100100100111511701601400388000080000801004004240042400424004240042
1602044004131303225240104801001600041001600205001440132140022400414004119977619992160120200160032200160032400414004111802011009910080100100103111511701600400388000080000801004004240042400424004240042
1602044004130003225240104801001600041001600205001440132140022400414004119977619992160120200160032200160032400414004111802011009910080100100200111511701600400388000080000801004004240042400424004240042
160204400413001232252401048010016000410016002050014401320400224004140041199776199921601202001604602001600324004140120118020110099100801001000012111511701600400388000080000801004004240042400424004240042

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

retire (01)cycle (02)031e3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696b6d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)9fa8acc2c5branch mispredict (cb)cdcfd2d5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
1600244005529904225240010800101600001016000050144189814002204004140041199963200211600102016000020160000400414004111800211091080010100900005020041625400388000080000800104004240042400424004240042
160024400413000422524001080010160000101600005014400000400220400414004119996320021160010201600002016000040041400411180021109108001010015000005020041642400388000080000800104004240042400424004240042
16002440041300042252400108001016000010160000501440000040022040041400411999632002116001020160000201600004004140041118002110910800101007200005020041646400388000080000800104004240042400424004240042
160024400413100422524001080104160000101600005014400000400220400414004119996320021160010201600002016000040041400411180021109108001010012900005020041642400388000080000800104004240042400424004240042
160024400413000256252400108001016000010160000501440000140022040041400411999632002116001020160000201600004004140041118002110910800101001520005020021634400388000080000800104004240042400424004240042
1600244004130004225240010800101600001016000050144000014002204004140041199963200211600102016000020160000400414004111800211091080010100000005020041642400388000080000800104004240042400424004240042
160024400413000422524001080010160000101600005014400000400220400414004119996320021160010201600002016000040041400411180021109108001010016800005020021624400388000080000800104004240042400424004240042
160024400412990883252400108001016000010160000501440000040022040041400411999632002116001020160000201600004004140041118002110910800101001800005020021642400388000080000800104004240042400424004240042
160024400412990422524001080010160000101600005014400000400220400414004119996320021160010201600002016000040041400411180021109108001010018000005020041624400388000080000800104004240042400424004240042
16002440041300042252400108001016000010160000501440000140022040041400411999632002116001020160000201600004004140041118002110910800101001800005020021624400388000080000800104004240042400424004240042