Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FCVTMU (scalar, S to X)

Test 1: uops

Code:

  fcvtmu x0, s0
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 3.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 2.000

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst int alu (97)l1d tlb access (a0)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
2004541404325300010002000200018000522541541248327420002000200054154111100110000007311611538100010001000542542542542542
2004541404325300010002000200018000522541541248327420002000200054154111100110000007311611538100010001000542542542542542
2004541404325300010002000200018000522541541248327420002000200054154111100110000007311611538100010001000542542542542542
2004541404325300010002000200018000522541541248327420002000200054154111100110000007311611538100010001000542542542542542
2004541404325300010002000200018000522541541248327420002000200054154111100110000007311611538100010001000542542542542542
2004541404325300010002000200018000522541541248327420002000200054154111100110000107311611538100010001000542542542542542
2004541404325300010002000200018000522541541248327420002000200054154111100110000007311611538100010001000542542542542542
2004541404325300010002000200018000522541541248327420002000200054154111100110000007311611538100010001000542542542542542
20045414124325300010002000200018000522541541248327420002000200054154111100110000037311611538100010001000542542542542542
2004541404325300010002000200018000522541541248327420002000200054154111100110000007311611538100010001000542542542542542

Test 2: Latency 1->2 roundtrip

Code:

  fcvtmu x0, s0
  fmov d0, x0
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 13.0038

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)0f18191e1f3a3f4f51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9abacc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd0l1i tlb miss demand (d4)d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
302041300389740020000013002311945925401001010020000100001002000010000500621497914801034113001301300381300381254763126246301002001000020000200100002000013003813003811202011009910010100100001000010000000000001310102162212952510000100001000010100130039130039130056130104130039
302041300389740000000013002311949925401001010020000100001002000010000500621497914801034113001301300381300381254763126246301002001000020000200100002000013004613003811202011009910010100100001000010000000000001335102162312952510000100001000010100130039130099130040130039130039
3020413003897400000120013002311941725401001010020000100001002000010000576621497914801034013001301300381300381254763126246301002001000020000200100002000013003813003811202011009910010100100001000010000000000001310102163212952510000100001000010100130039130039130075130044130039
302041300389740000000013002311941725401001010020000100001002000010000500621497914801034013001301300381300381254763126246301002001000020000200100002000013003813003811202021009910010100100001000010000000000001310102162212952510000100001000010100130039130039130134130044130039
302041300389730000000013002311941825401001010020000100001002000010000500621497914801034013001301300381300381254763126246301002001000020000200100002000013003813003811202011009910010100100001000010000000000001310102162212952510000100001000010100130039130039130106130040130039
302041300389740000000013002311941725401001010020000100001002000010000500621497914801034013001301300381300381254763126246301002001000020000200100002000013003813003811202011009910010100100001000010000000000001310102161212952510000100001000010100130039130039130097130043130069
302041300389740000060013002311941725401001010020000100001002000010000500621497914801034113001301300381300381254763126246301002001000020000200100002000013003813003811202011009910010100100001000010000000000001310102162212952510000100001000010100130039130039130124130042130039
302041300389740000000013002311941725401001010020000100001002000010000500621497914801034113001301300381300381254763126246301002001000020000200100002000013003813003811202011009910010100100001000010000000000001310002162212952510000100001000010100130039130039130088130039130039
302041300389740000000013002311941725401001010020000100001002000010000500621497914801034013001301300381300381254763126246301002001000020000200100002000013003813003811202011009910010100100001000010000000000001310102162212952510000100001000010100130039130039130103130044130039
3020413003897400000000130023119437254010010100200001000010020000100005006214979148010341130013013003813003812547631262463010020010000200002001000020000130038130038112020110099100101001000010000100000003300001310102162212952510000100001000010100130039130116130089130041130040

1000 unrolls and 10 iterations

Result (median cycles for code): 13.0038

retire uop (01)cycle (02)031e3f4f51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
300241300389730130023119417254001010010200001000010200001000050621497914800025013001313003813003812549831262683001020100002000020100002000013003813003811200221091010010100001001000000012702181112952510000100001000010010130039130039130039130039130039
300241300389740130023119417254001010010200001000010200001000050621497914800025113001313003813003812549831262683001020100002000020100002000013003813003811200211091010010100001001000000012701161112952510000100001000010010130083130039130039130039130039
300241300389740130023119417254001010010200001000010200001000050621497914800025113001313003813003812549831262683001020100002000020100002000013003813003811200211091010010100001001000000012701161212952510000100001000010010130039130039130039130039130039
300241300389740130023119417254001010010200001000010200001000050621497914800025113001313003813003812549831262683001020100002012620100002000013003813003811200211091010010100001001000000012701161112952510000100001000010010130039130039130039130039130039
300241300389740130023119417254001010010200001000010200001000050621497914800025113001313003813003812549831262683001020100002048120100002000013003813004611200211091010010100001021000000012701161212952510000100001000010010130039130039130039130039130039
300241300389730130023119417254001710010200001000010200001000050621497914800025013001313003813003812549831262683001020100002000020100002000013003813003811200211091010010100001001000000012701161112952510000100001000010010130039130039130039130039130039
300241300389740130023119417254001010010200001000010200001000050621497914800025113001313003813003812549831262683001020100002000020100002000013003813003811200211091010010100001001000003012701161112952510000100001000010010130039130039130039130039130039
300241300389740130023119417254001010010200001000010200001000050621497914800025113001313003813004012549831262683001020100002000020100002000013003813003811200211091010010100001001000000012701161112952510000100001000010010130039130039130039130039130039
300241300389740130023119417254001010010200001000010200001000050621497914800025013001313003813003812549831262683001020100002000020100002000013003813003811200211091010010100001001000000012701161112952510000100001000010010130039130070130039130039130039
300241300389730130023119417254001010010200001000010200001000050621497914800025113001313003813003812549831262683001020100002048120100002000013003813003811200211091010010100001001000000012701161112952510000100001000010010130039130039130039130039130039

Test 3: throughput

Count: 8

Code:

  fcvtmu x0, s8
  fcvtmu x1, s8
  fcvtmu x2, s8
  fcvtmu x3, s8
  fcvtmu x4, s8
  fcvtmu x5, s8
  fcvtmu x6, s8
  fcvtmu x7, s8
  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
160204400663210742524010480100160004100160020500144013204002240041400411997761999216012020016003220016003240041400411180201100991008010010000000111511701600400388000080000801004004240042400424004240042
160204400413100322524010480100160004100160020500144013204002240041400411997761999216012020016003220016003240041400411180201100991008010010000000111511701600400388000080000801004004240042400424004240042
160204400413100442524010480100160004100160020500144013214002240041400411997761999216012020016003220016003240041400411180201100991008010010000000111511701600400388000080000801004004240042400424004240042
1602044004131001502524010480100160004100160020500144013214002240041400411997761999216012020016003220016003240041400411180201100991008010010000000111511701600400388000080000801004004240042400424004240042
160204400413100322524010480100160004100160020500144013204002240041400411997761999216012020016003220016003240041400411180201100991008010010000000111511701600400388000080000801004004240042400424004240042
160204400413110322524010480100160004100160020500144013204002240041400411997761999216012020016003220016003240041400411180201100991008010010000000111511701600400388000080000801004004240042400424004240042
160204400413100322524010480100160004100160020500144013214002240041400411997761999216012020016003220016003240041400411180201100991008010010000000111511701600400388000080000801004004240042400424004240042
160204400413100322524010480100160004100160020500144013204002240041400411997761999216012020016003220016003240041400411180201100991008010010000000111511701600400388000080000801004004240042400424004240042
160204400413100322524010480100160004100160020500144013204002240041400411997761999216012020016003220016003240041400411180201100991008010010000000111511701600400388000080000801004004240042400424004240042
160204400413110322524010480100160004100160020500144013204002240041400411997761999216012020016003220016003240041400411180201100991008010010000000111511701600400388000080000801004004240042400424004240042

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

retire uop (01)cycle (02)030918191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap stall dispatch (70)rob full (74)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb miss (a1)acbranch mispred nonspec (cb)cfd5map dispatch bubble (d6)daddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
160024400433000000042252400108001016000010160000501440000014002240041400411999603200211600102016000020160236400414004111800211091080010100005020171601715400388000080000800104004240042400424004240042
1600244004130000000422252400108001016000010160000501440000004002240041400411999603200211600102016000020160000400414004111800211091080010100005020171601115400388000080000800104004240042400424004240042
160024400413000000042252400108001016000010160000501440000014002240041400411999603200211600102016000020160000400414004111800211091080010100005020171601914400388000080000800104004240042400424004240042
1600244004130000000407252400108001016000010160000501440000014002240041400411999603200211600102016000020160000400414004111800211091080010100005020171601613400388000080000800104004240042400424004240042
160024400412990000042252400108001016000010160000501440000014002240041400411999603200211600102016000020160000400414004111800211091080010100005020141601413400388000080000800104004240042400424004240042
160024400413000000042252400108001016000010160000501440000014002240041400411999603200211600102016000020160000400414004111800211091080010100005020141601317400388000080000800104004240042400424004240042
160024400412990000042252400108001016000010160000501440000014002640041400411999603200211600102016000020160000400414004111800211091080010100005020161601914401028000080000800104004240042400424004240042
160024400413000000042252400108001016000010160000501440000014002240041400411999603200211600102016000020160000400414004111800211091080010100005020181611217400388000080000800104004240042400424004240042
1600244004130000215042252400108001016000010160000501440000014002240041400411999603200211600102016000020160000400414004111800211091080010100005020181601316400388000080000800104004240042400424004240042
160024400413000000042252400108001016000010160000501440000014002240041400411999603200211600102016000020160000400414004111800211091080010100005020141601815400388000080000800104004240042400424004240042