Firestorm: FCVTN2 (vector, 2D) measurements

Code:

  fcvtn2 v0.4s, v1.2d

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	3037	24	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	0	73	0	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	24	93	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	0	73	0	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	24	48	131	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	0	73	0	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	24	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	0	73	0	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	24	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	0	73	0	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	24	81	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	0	73	0	2	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	0	73	0	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	24	36	84	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	0	73	0	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	61	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	0	73	0	1	16	1	1	2630	1000	3038	3038	3038	3038	3038
1004	3037	24	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	0	73	0	1	16	1	1	2630	1000	3038	3038	3038	3038	3038

Test 2: Latency 1->1

Code:

  fcvtn2 v0.4s, v1.2d

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	18	1e	1f	22	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	233	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30182	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	1	9	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	232	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	233	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	1	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	233	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30086	30084	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	1	48	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	233	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	3	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	233	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	4	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	233	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	233	0	0	0	0	0	0	103	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	212	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	233	0	0	0	0	0	0	61	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	1	9	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	233	0	0	69	0	0	0	103	29548	25	10100	100	10000	100	10000	500	4277313	0	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	710	1	16	1	1	29670	0	10000	100	30133	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	233	0	536	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	233	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	233	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	233	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30179	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	233	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	232	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	233	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	18	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	233	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	232	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	2	0	0	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038
10024	30037	233	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	10000	20	20000	30084	30037	1	1	10021	10	9	10	10	10000	10	0	0	3	640	2	16	2	2	29630	10000	10	30038	30038	30038	30038	30038

Test 3: Latency 1->2

Code:

  fcvtn2 v0.4s, v0.2d

Initialization

  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	233	0	0	0	0	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	0	30018	30037	30037	28271	7	28741	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	718	0	16	0	0	29646	0	10000	100	30038	30038	30038	30038	30038
10204	30037	233	0	0	0	0	0	0	61	29547	44	10100	100	10000	100	10000	500	4277160	0	30018	30037	30037	28271	6	28740	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	718	0	16	0	0	29646	0	10000	100	30038	30038	30038	30038	30038
10204	30085	247	0	0	0	0	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	1	30018	30037	30037	28271	6	28741	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	719	0	16	0	0	29645	0	10000	100	30038	30038	30038	30038	30038
10204	30037	233	0	0	0	0	0	0	251	29547	25	10100	100	10000	100	10000	500	4277160	1	30018	30037	30037	28271	6	28740	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	1	0	1	1	1	717	0	16	0	0	29645	0	10000	100	30038	30038	30038	30038	30038
10204	30037	233	0	0	0	0	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	1	30018	30037	30037	28271	6	28741	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	717	0	16	0	0	29646	0	10000	100	30038	30038	30038	30038	30038
10204	30037	233	0	0	0	0	0	0	156	29547	25	10100	100	10000	100	10000	500	4277160	0	30018	30037	30037	28271	6	28741	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	1	0	1	1	1	718	0	16	0	0	29645	0	10000	100	30038	30038	30038	30038	30038
10204	30037	233	0	0	0	0	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	1	30018	30037	30037	28271	6	28741	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	1	0	1	1	1	718	0	16	0	0	29645	0	10000	100	30038	30038	30038	30038	30038
10204	30037	232	0	0	0	0	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	0	30018	30037	30037	28271	7	28740	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	1	0	1	1	1	718	0	16	0	0	29645	0	10000	100	30038	30038	30038	30038	30038
10204	30037	233	0	0	0	0	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	1	30018	30037	30037	28271	7	28741	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	1	0	1	1	1	717	0	16	0	0	29646	0	10000	100	30038	30038	30038	30038	30038
10204	30037	232	0	0	0	0	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	0	30018	30037	30037	28271	6	28741	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	1	1	1	718	0	16	0	0	29646	0	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	233	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	1	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	233	12	0	232	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	233	21	0	61	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	3	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	233	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	233	3	0	61	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	233	0	0	726	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	232	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	233	0	0	75	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	4	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10024	30037	233	0	88	105	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038
10025	30037	233	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	640	2	16	2	2	29629	10000	10	30038	30038	30038	30038	30038

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  fcvtn2 v0.4s, v8.2d
  movi v1.16b, 0
  fcvtn2 v1.4s, v8.2d
  movi v2.16b, 0
  fcvtn2 v2.4s, v8.2d
  movi v3.16b, 0
  fcvtn2 v3.4s, v8.2d
  movi v4.16b, 0
  fcvtn2 v4.4s, v8.2d
  movi v5.16b, 0
  fcvtn2 v5.4s, v8.2d
  movi v6.16b, 0
  fcvtn2 v6.4s, v8.2d
  movi v7.16b, 0
  fcvtn2 v7.4s, v8.2d

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2510

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	20088	155	0	222	25	80116	100	80016	100	80028	500	640196	1	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10119	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	156	0	220	25	80116	100	80016	100	80028	500	640196	1	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10119	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	156	0	159	25	80116	100	80016	100	80028	500	640196	1	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10119	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	155	0	192	25	80116	100	80016	100	80028	500	640196	1	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20150	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10169	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	155	0	29	25	80116	100	80016	100	80028	500	640196	1	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10119	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	155	0	823	25	80116	100	80016	100	80028	500	640196	1	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10119	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	156	0	1004	25	80116	100	80016	100	80028	500	640196	1	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10119	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	155	0	454	25	80116	100	80016	100	80028	500	640196	1	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10119	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	155	0	250	25	80116	100	80016	100	80028	500	640196	1	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10119	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	155	0	220	25	80116	100	80016	100	80028	500	640196	1	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	1	1	1	10119	0	16	0	0	20062	160000	100	20066	20066	20066	20066	20066

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	a9	ac	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	eb	ec	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	20081	156	0	51	25	80010	10	80000	10	80000	50	640000	0	1	0	20031	20050	20050	3	22	80010	20	80000	20	160000	20046	20050	1	1	160021	10	9	10	10	160000	10	0	0	0	10042	8	1	1	12	20	2	1	1	14	6	20043	15	0	112	160000	10	20047	20047	20047	20047	20047
160024	20046	155	0	45	25	80010	10	80000	10	80000	50	640000	1	1	5	20027	20046	20046	3	22	80010	20	80000	20	160000	20046	20046	1	1	160021	10	9	10	10	160000	10	0	0	0	10034	8	5	1	7	20	2	1	1	8	16	20043	15	0	89	160000	10	20047	20047	20047	20047	20047
160024	20046	155	0	45	25	80010	10	80000	10	80000	50	640000	1	1	5	20027	20046	20046	3	22	80010	20	80000	20	160000	20046	20046	1	1	160021	10	9	10	10	160000	10	0	0	0	10028	8	5	1	4	20	2	1	1	9	9	20043	15	0	84	160000	10	20047	20047	20047	20047	20047
160024	20046	155	0	45	25	80010	10	80000	10	80000	50	640000	1	1	5	20027	20046	20046	3	22	80010	20	80000	20	160000	20046	20046	1	1	160021	10	9	10	10	160000	10	0	0	0	10033	8	5	1	6	20	2	1	1	6	9	20043	15	0	82	160000	10	20047	20047	20047	20047	20047
160024	20046	155	0	45	25	80010	10	80000	10	80000	50	640000	1	1	5	20027	20046	20046	3	22	80010	20	80000	20	160000	20046	20046	1	1	160021	10	9	10	10	160000	10	0	0	0	10030	8	5	1	10	20	2	1	1	13	5	20043	15	0	100	160000	10	20047	20047	20047	20047	20047
160024	20046	155	0	45	25	80010	10	80000	10	80000	50	640000	1	1	5	20027	20046	20046	3	22	80010	20	80000	20	160000	20046	20046	1	1	160021	10	9	10	10	160000	10	0	0	0	10038	8	5	1	10	20	2	1	1	7	10	20043	15	0	77	160000	10	20047	20047	20047	20047	20047
160024	20046	155	0	45	25	80010	10	80000	10	80000	50	640000	1	1	5	20027	20046	20046	3	22	80010	20	80000	20	160000	20046	20046	1	1	160021	10	9	10	10	160000	10	0	0	0	10029	8	5	1	13	20	2	1	1	7	10	20043	15	0	75	160000	10	20047	20047	20047	20047	20047
160024	20046	155	9	45	29	80010	10	80000	10	80000	50	640000	0	1	0	20041	20060	20060	3	22	80010	20	80000	20	160000	20051	20060	1	1	160021	10	9	10	10	160000	10	0	0	0	10029	3	1	1	15	25	2	1	1	9	6	20048	20	75	4	160000	10	20052	20052	20052	20052	20052
160024	20051	155	0	45	27	80010	10	80000	10	80000	50	640000	1	1	0	20032	20051	20051	3	22	80010	20	80000	20	160000	20051	20051	1	1	160021	10	9	10	10	160000	10	0	0	0	10033	3	1	1	15	25	2	1	1	10	7	20048	20	69	8	160000	10	20052	20052	20052	20052	20052
160024	20051	155	0	101	27	80010	10	80000	10	80000	50	640000	1	1	0	20032	20051	20051	3	22	80010	20	80000	20	160000	20051	20051	1	1	160021	10	9	10	10	160000	10	0	0	0	10033	3	1	1	10	27	2	1	1	10	7	20048	20	61	4	160000	10	20061	20061	20052	20061	20061

Test 5: throughput

Count: 16

Code:

  fcvtn2 v0.4s, v16.2d
  fcvtn2 v1.4s, v16.2d
  fcvtn2 v2.4s, v16.2d
  fcvtn2 v3.4s, v16.2d
  fcvtn2 v4.4s, v16.2d
  fcvtn2 v5.4s, v16.2d
  fcvtn2 v6.4s, v16.2d
  fcvtn2 v7.4s, v16.2d
  fcvtn2 v8.4s, v16.2d
  fcvtn2 v9.4s, v16.2d
  fcvtn2 v10.4s, v16.2d
  fcvtn2 v11.4s, v16.2d
  fcvtn2 v12.4s, v16.2d
  fcvtn2 v13.4s, v16.2d
  fcvtn2 v14.4s, v16.2d
  fcvtn2 v15.4s, v16.2d

Initialization

  movi v16.16b, 17

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2502

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5e	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	40058	310	0	1	0	72	25	160108	100	160008	100	160020	500	1280132	81	1	40143	40039	40039	19977	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	0	1	1	1	10118	1	16	1	1	40036	160000	100	40040	40040	40040	40040	40040
160204	40039	310	1	1	0	30	25	160108	100	160008	100	160020	500	1280132	0	0	40020	40039	40039	19977	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	0	1	1	1	10118	1	16	1	1	40036	160000	100	40040	40040	40040	40040	40040
160204	40039	310	1	1	0	30	25	160108	100	160008	100	160020	500	1280132	0	0	40020	40039	40039	19977	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	0	1	1	1	10118	1	16	1	1	40036	160000	100	40040	40040	40040	40040	40040
160204	40039	310	1	1	0	30	25	160108	100	160008	100	160020	500	1280132	0	1	40020	40039	40039	19977	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	0	1	1	1	10118	1	16	1	1	40036	160000	100	40040	40040	40040	40040	40040
160204	40039	310	1	1	0	30	25	160108	100	160008	100	160020	500	1280132	0	0	40020	40039	40039	19977	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	0	1	1	1	10118	1	16	1	1	40036	160000	100	40040	40040	40040	40040	40040
160204	40039	310	1	1	12	135	25	160108	100	160108	100	160020	500	1280132	0	1	40020	40039	40039	19977	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	0	1	1	1	10118	1	16	1	1	40036	160000	100	40040	40040	40040	40040	40040
160204	40039	310	1	1	0	30	25	160108	100	160008	100	160020	500	1280132	0	1	40020	40039	40039	19977	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	0	1	1	1	10118	1	16	1	1	40036	160000	100	40040	40040	40040	40040	40040
160204	40039	310	1	1	0	30	25	160108	100	160008	100	160020	500	1280132	0	1	40020	40039	40039	19977	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	8	0	1	1	1	10118	1	16	3	1	40036	160000	100	40040	40040	40040	40040	40040
160204	40039	310	1	1	0	30	25	160108	100	160008	100	160020	500	1280132	0	1	40020	40039	40039	19977	6	19990	160120	200	160032	200	320278	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	0	1	1	1	10118	1	16	1	1	40036	160000	100	40040	40040	40040	40040	40040
160204	40039	311	1	1	0	30	25	160108	100	160008	100	160020	500	1280132	0	1	40020	40039	40039	19977	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	0	1	1	1	10118	1	16	1	1	40036	160000	100	40040	40040	40040	40040	40040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2502

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cd	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d7	d9	da	db	dd	fetch restart (de)	e0	ea	eb	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	40039	310	0	0	0	0	0	0	46	25	160010	10	160000	10	160000	50	1280000	1	1	40020	40039	40039	19996	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	10022	3	1	1	6	16	0	4	2	1	5	6	40036	40	6	160000	10	40040	40040	40040	40040	40040
160024	40039	311	0	0	0	0	0	0	74	25	160010	10	160000	10	160000	50	1280000	1	1	40020	40039	40039	19996	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	10024	6	2	2	6	16	0	4	2	2	6	4	40036	20	12	160000	10	40040	40040	40040	40040	40040
160024	40039	310	0	0	0	0	0	0	52	25	160010	10	160000	10	160000	50	1280000	0	1	40020	40039	40039	19996	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	10022	6	2	2	8	16	0	4	2	2	6	9	40036	40	12	160000	10	40040	40040	40040	40040	40040
160024	40039	322	0	0	0	0	0	0	52	25	160010	10	160000	10	160000	50	1280000	0	1	40020	40039	40039	19996	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	10022	6	2	1	6	16	0	2	1	2	5	6	40036	40	12	160000	10	40040	40040	40040	40040	40040
160024	40039	310	0	0	0	0	0	0	69	25	160010	10	160000	10	160000	50	1280000	0	1	40020	40039	40039	19996	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	10022	3	1	1	8	16	0	2	1	1	9	9	40036	40	12	160000	10	40040	40040	40040	40040	40040
160024	40039	311	0	0	0	0	0	0	717	25	160010	10	160000	10	160000	50	1280000	0	1	40020	40039	40039	19996	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	10024	6	2	2	6	16	0	4	2	1	6	4	40036	40	12	160000	10	40040	40040	40040	40040	40040
160024	40039	310	0	0	0	0	0	0	46	25	160010	10	160000	10	160000	50	1280000	1	1	40020	40039	40039	19996	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	10022	3	1	1	6	16	0	2	1	1	5	6	40036	20	6	160000	10	40040	40040	40040	40040	40040
160024	40039	310	0	0	0	0	0	0	46	25	160010	10	160000	10	160000	50	1280000	1	1	40020	40039	40039	19996	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	10022	3	1	1	6	16	0	2	1	1	8	5	40036	20	6	160000	10	40040	40040	40040	40040	40040
160024	40039	310	0	0	0	0	0	0	52	25	160010	10	160000	10	160000	50	1280000	1	1	40020	40039	40039	19996	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	10024	6	2	2	6	16	0	4	2	2	9	9	40036	40	6	160000	10	40040	40040	40040	40040	40040
160024	40039	311	0	0	0	0	30	0	1490	25	160010	10	160000	10	160000	50	1280000	0	1	40020	40039	40039	19996	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	0	0	0	10022	6	1	2	8	16	0	4	2	2	4	11	40036	20	12	160000	10	40040	40040	40040	40040	40040

FCVTN2 (vector, 2D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations