Firestorm: FCVTNS (scalar, D to W) measurements

Code:

  fcvtns w0, d0

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 3.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 2.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	l1d cache writeback (a8)	a9	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
2004	541	4	0	0	43	25	3000	1000	2000	2000	18000	0	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	1	0	0	0	73	1	16	1	1	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	0	43	25	3000	1000	2000	2000	18000	0	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	0	0	73	1	16	1	1	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	0	43	25	3000	1000	2000	2000	18000	0	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	0	0	73	1	16	1	1	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	0	43	25	3000	1000	2000	2000	18000	1	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	0	0	73	1	16	1	1	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	12	43	25	3000	1000	2000	2000	18000	0	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	3	0	73	1	16	1	1	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	0	43	25	3000	1000	2000	2000	18000	0	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	4	3	0	73	1	16	1	1	538	1000	1000	1000	542	542	542	542	542
2004	541	5	1	0	138	48	3000	1000	2000	2000	18000	0	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	3	4	73	1	16	1	1	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	0	43	25	3000	1000	2000	2000	18000	0	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	0	0	73	1	16	1	1	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	0	43	25	3000	1000	2000	2000	18000	0	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	0	0	73	1	16	1	1	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	0	85	25	3000	1000	2000	2000	18000	1	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	0	0	73	1	16	1	1	538	1000	1000	1000	542	542	542	542	542

Test 2: Latency 1->2 roundtrip

Code:

  fcvtns w0, d0
  fmov d0, x0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 13.0038

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	18	19	1e	1f	3a	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	61	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30204	130038	974	0	0	0	0	0	0	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	0	2	130013	0	130038	130038	125476	3	126246	30100	200	10000	20000	200	10000	20000	130038	130078	5	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	0	0	1310	1	2	16	2	2	129525	10000	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	974	0	0	0	0	0	0	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	0	0	130013	0	130038	130074	125476	3	126246	30100	200	10000	20000	200	10000	20000	130097	130057	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	0	0	1310	1	2	16	2	2	129525	10000	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	974	0	0	0	0	0	0	0	130024	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	0	0	130013	0	130038	130038	125476	3	126246	30100	200	10000	20000	200	10000	20000	130038	130104	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	0	0	1310	1	2	16	2	2	129525	10000	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	974	0	0	0	0	0	0	0	130024	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	0	0	130013	0	130038	130038	125476	3	126246	30284	200	10000	20000	200	10000	20000	130038	130092	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	0	0	1310	1	2	16	2	2	129525	10000	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	974	0	0	0	0	0	0	0	130023	119417	25	40100	10100	20000	10001	100	20000	10000	500	6214979	14801034	0	5	130013	3	130038	130038	125476	3	126246	30100	200	10000	20000	200	10064	20000	130038	130086	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	0	0	1310	1	2	16	2	2	129525	10000	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	974	0	0	0	0	0	0	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	0	0	130013	0	130038	130038	125476	3	126246	30100	200	10000	20000	200	10000	20000	130038	130081	5	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	0	1	1310	1	2	16	2	2	129525	10000	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	974	0	0	0	0	3	0	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	0	0	130013	0	130038	130038	125476	3	126246	30100	200	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	1	0	1310	1	2	16	2	2	129525	10000	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	974	0	0	0	0	0	0	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	0	0	130013	0	130038	130038	125476	20	126253	30100	200	10000	20000	200	10000	20000	130038	130091	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	0	0	1310	1	2	16	2	2	129525	10000	10000	10000	10100	130039	130039	130039	130039	130074
30204	130039	974	0	0	0	0	0	0	0	130023	119408	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	0	0	130013	0	130038	130038	125476	3	126246	30100	200	10000	20000	200	10000	20000	130038	130104	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	0	0	1310	1	2	16	2	2	129525	10000	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	974	0	0	0	0	0	0	0	130023	119420	25	40100	10103	20000	10000	100	20000	10000	500	6214979	14801034	0	0	130013	0	130038	130038	125476	3	126246	30100	200	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	0	0	1310	1	2	16	2	2	129525	10000	10000	10000	10100	130039	130039	130039	130039	130039

1000 unrolls and 10 iterations

Result (median cycles for code): 13.0038

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30024	130039	974	0	0	0	0	0	0	0	0	0	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	0	130013	130038	130038	125498	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	0	1270	2	16	2	2	129525	10000	0	10000	10000	10010	130091	130064	130039	130039	130039
30024	130038	974	0	0	0	0	0	0	0	0	0	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	0	130013	130038	130038	125498	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	0	1270	2	16	2	2	129525	10000	0	10000	10000	10010	130042	130058	130039	130046	130039
30024	130038	974	0	0	0	0	0	0	0	0	0	130023	119421	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	0	130013	130038	130038	125498	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	0	0	10088	0	2	200045	0	0	1851	4	272	4	8	131190	10004	137	10000	10000	10010	130044	130039	130050	130039	130046
30024	130038	974	0	0	0	0	0	0	0	0	0	130023	119417	25	40010	10010	20000	10000	13	20466	10000	50	6214979	14800025	1	130013	130359	130038	125498	3	126481	30010	20	10000	20476	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	0	1270	2	16	2	2	129525	10000	0	10000	10000	10010	130372	130068	130039	130042	130039
30024	130038	974	0	0	0	0	0	0	0	0	1	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	0	130013	130038	130038	125498	3	126268	30010	20	10000	20000	22	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	2	0	10000	0	0	9	0	0	1270	2	50	2	2	129528	10000	0	10000	10000	10010	130040	130039	130040	130043	130039
30024	130039	976	0	0	0	0	0	0	0	0	0	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14820445	0	130013	130038	130038	125498	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	0	1270	2	16	2	2	129525	10000	0	10000	10000	10010	130068	130047	130039	130039	130039
30024	130038	974	0	0	0	0	0	0	0	0	0	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	0	130013	130038	130038	125498	3	126268	30010	20	10000	20000	20	10000	20482	130038	130038	1	1	20021	10	9	10	10010	10000	10	0	0	10000	1	0	0	0	0	1270	2	16	2	2	129525	10005	0	10000	10000	10010	130053	130039	130039	130039	130039
30024	130038	974	0	0	0	0	0	0	12	352	0	130023	119554	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	0	130013	130038	130038	125498	3	126268	30010	22	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	0	1270	2	16	3	2	129528	10000	0	10000	10000	10010	130060	130040	130039	130039	130039
30024	130039	974	0	0	0	0	4	0	0	0	0	130023	119417	25	40010	10010	20000	10000	10	20466	10000	50	6214979	14800025	0	130013	130038	130038	125499	3	126268	30010	20	10000	20000	20	10000	20000	130038	130374	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	17147	0	0	1270	2	16	2	2	129525	10000	0	10000	10000	10010	130041	130383	130039	130064	130039
30024	130038	974	0	1	0	0	0	0	0	0	0	130023	119418	25	40010	10010	20000	10000	10	20000	10098	50	6214979	14800025	0	130015	130038	130038	125498	9	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	2	0	10000	0	0	9	0	0	1270	2	50	2	2	129525	10000	0	10000	10000	10010	130468	130043	130039	130044	130039

Test 3: throughput

Count: 8

Code:

  fcvtns w0, d8
  fcvtns w1, d8
  fcvtns w2, d8
  fcvtns w3, d8
  fcvtns w4, d8
  fcvtns w5, d8
  fcvtns w6, d8
  fcvtns w7, d8

Initialization

  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	40041	299	0	0	0	0	0	0	0	32	25	240104	80100	160004	100	160020	500	1440132	0	40022	40041	40041	19977	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	1	1	1	5117	0	16	0	0	40038	80000	80000	80100	40042	40042	40042	40042	40042
160204	40041	300	0	0	0	0	0	0	0	32	25	240104	80100	160004	100	160020	500	1440132	0	40022	40041	40041	19977	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	1	1	1	5117	0	16	0	0	40038	80000	80000	80100	40042	40042	40042	40042	40042
160204	40041	300	0	0	0	0	0	0	0	32	25	240104	80100	160004	100	160020	500	1440132	0	40022	40041	40041	19977	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	1	1	1	5117	0	16	0	0	40038	80000	80000	80100	40042	40042	40042	40042	40042
160204	40041	299	0	0	0	0	0	0	0	32	25	240104	80100	160004	100	160020	500	1440132	0	40022	40041	40041	19977	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	1	1	1	5117	0	16	0	0	40038	80000	80000	80100	40042	40042	40042	40042	40042
160204	40207	314	0	0	0	0	0	0	0	802	25	240104	80100	160004	100	160020	500	1440132	0	40022	40041	40041	19977	14	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	1	1	1	5117	0	16	0	0	40038	80000	80000	80100	40042	40042	40042	40042	40042
160204	40041	300	0	0	0	0	0	0	0	74	25	240104	80100	160004	100	160020	500	1440132	0	40022	40041	40041	19977	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	1	1	1	5117	1	16	0	0	40038	80000	80000	80100	40042	40042	40042	40042	40042
160204	40041	300	0	0	0	0	0	0	0	259	25	240104	80100	160004	100	160020	500	1440132	0	40022	40041	40041	19977	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	0	1	0	0	0	1	1	1	5117	0	16	0	0	40038	80000	80000	80100	40042	40042	40042	40042	40042
160204	40041	300	0	0	0	0	0	12	0	74	25	240104	80100	160004	100	160020	500	1440132	0	40022	40041	40041	19977	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	0	0	0	3	0	1	1	1	5117	0	16	0	0	40038	80188	80000	80100	40042	40042	40042	40042	40201
160204	40041	300	0	0	1	0	0	0	0	32	25	240378	80100	160400	100	160020	500	1440132	0	40022	40041	40041	19977	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	1	1	1	5117	0	16	0	0	40038	80000	80000	80100	40042	40042	40042	40042	40042
160204	40041	310	0	0	0	0	0	0	0	32	25	240104	80100	160004	100	160020	500	1440132	0	40022	40041	40041	19977	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	0	0	0	3	0	1	1	1	5117	0	16	0	0	40038	80000	80000	80100	40042	40042	40042	40042	40042

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	rob full (74)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	c2	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	eb	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	41067	309	2	1	1	0	0	0	0	1828	187	241732	81062	161358	10	161428	50	1452544	0	40719	40673	40681	20210	0	58	20427	161434	20	162228	20	161784	40762	41220	7	1	80021	10	9	10	80010	10	2	0	1235	4	0	5303	0	4	205	2	8	40948	81399	0	80000	80010	40284	40198	40042	40042	41401
160024	41010	319	0	0	0	2	2	2760	1012	57	25	240010	80010	160000	10	160000	50	1440000	0	40022	40041	40041	19996	0	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5020	0	2	16	1	1	40038	80000	0	80000	80010	40042	40042	40042	40042	40042
160024	40041	299	0	0	0	0	0	0	0	42	25	240010	80010	160000	10	160000	50	1440000	0	40022	40041	40041	19996	0	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5020	0	2	16	1	1	40038	80000	0	80000	80010	40042	40042	40042	40042	40042
160024	40041	299	0	0	0	0	0	0	0	42	25	240010	80010	160000	10	160000	50	1440000	0	40022	40041	40041	19996	0	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5020	0	1	16	1	2	40038	80000	0	80000	80010	40042	40042	40042	40042	40042
160024	40041	300	0	0	0	0	0	0	0	42	25	240010	80010	160000	10	160000	50	1440000	0	40022	40041	40041	19996	0	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5020	0	1	16	1	1	40038	80000	0	80000	80010	40042	40042	40042	40042	40042
160024	40041	300	0	0	0	0	0	0	0	42	25	240010	80010	160000	10	160000	50	1440000	0	40022	40041	40041	19996	0	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	3	0	0	5020	0	1	16	1	1	40038	80000	14	80000	80010	40042	40042	40042	40042	40042
160024	40041	300	0	0	0	0	0	0	0	42	25	240010	80010	160000	10	160000	50	1440000	0	40022	40041	40041	19996	0	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5020	0	1	16	1	1	40038	80000	0	80000	80010	40042	40042	40042	40042	40042
160025	40041	300	0	0	0	0	0	0	0	42	25	240010	80010	160000	10	160000	50	1440000	0	40022	40041	40041	19996	0	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	1	0	0	0	5020	0	1	16	1	1	40038	80000	0	80000	80010	40042	40042	40042	40042	40042
160024	40041	300	0	0	0	0	0	0	0	42	25	240010	80010	160000	10	160000	50	1440000	0	40022	40041	40041	19996	0	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5020	0	1	16	1	1	40038	80000	0	80000	80010	40042	40042	40042	40042	40042
160024	40041	300	0	0	0	0	0	0	0	42	25	240010	80010	160000	10	160000	50	1440000	0	40022	40041	40041	19996	0	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	0	0	0	5020	0	1	16	1	3	40038	80000	0	80000	80010	40042	40042	40042	40042	40042

FCVTNS (scalar, D to W)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations