Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FCVTNS (scalar, H to H)

Test 1: uops

Code:

  fcvtns h0, h0
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10043037240000000842547251000100010003981603018303730372414328951000100010003037303711100110000000000073116112629100030383038303830383038
100430372300000001702547251000100010003981603018303730372414328951000100010003037303711100110000000000073116112629100030383038303830383038
10043037230000000612547251000100010003981603018303730372414328951000100010003037303711100110000000000073116112629100030383038303830383038
10043037230000000612547251000100010003981603018303730372414328951000100010003037303711100110000000000073116112629100030383038303830383038
10043037240000000612547251000100010003981603018303730372414328951000100010003037303711100110000000003073116112629100030383038303830383038
10043037240000000612547251000100010003981603018303730372414328951000100010003037303711100110000000100073116112629100030383038303830383038
10043037230000000612547251000100010003981603018303730372414328951000100010003037303711100110000000000073116112629100030383038303830383038
10043037230000000612547251000100010003981603018303730372414328951000100010003037303711100110000000000073116112629100030383038303830383038
1004303724000000061254725100010001000398160305430733084241482907115010001161308530842110011000400112418094124112645100030863085303830853085
100430842400111448805302547431008100011283995123054303730832418729141150116310963084308421100110001000002845073116112664100030853085308530843085

Test 2: Latency 1->2

Code:

  fcvtns h0, h0
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)0318191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fst unit uop (a7)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020430037233000089295472510100100100001001000050042771601300183003730037282643287451010020010000200100003003730037111020110099100100100001000007101161129633100001003003830038300383003830038
1020430037233000061295472510100100100001001000050042771601300183003730037282643287451010020010000200100003003730037111020110099100100100001000007101161129633100001003003830038300383003830038
1020430037241000061295472510100100100001001000050042771601300183003730037282643287451010020010000200100003003730037111020110099100100100001000007101161129633100001003003830038300383003830038
1020430037233002717661295472510100100100001001000050042771601300183003730037282643287451010020010000200100003003730037111020110099100100100001000007101161129633100001003003830038300383003830038
1020430037233010061295472510100100100001001000050042771601300183003730037282643287451010020010000200100003003730037111020110099100100100001000007101161129633100001003003830038300383003830038
1020430037233000061295472510100100100001001000050042771601300183003730037282643287451010020010000200100003003730037111020110099100100100001000037101161129633100001003003830038300383003830038
1020430037233000061295472510100100100001001000050042771601300183003730037282643287451010020010000200100003003730037111020110099100100100001000007101161129633100001003003830038300383003830038
1020430037233000061295472510100100100001001000050042771601300183003730037282643287451010020010000200100003003730037111020110099100100100001000007101161129633100001003003830038300383003830038
10204300372330000726295472510100100100001001000050042771601300183003730037282643287451010020010000200100003003730037111020110099100100100001000007101161129633100001003003830038300383003830038
1020430037233000061295472510100100100001001000050042771601300183003730037282643287451010020010000200100003003730037111020110099100100100001000007101161129633100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)0309191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002430037225000712954725100101010000101000050427716013001830037300372828632876710010201000020100003003730037111002110910101000010000640316222962910000103003830038300383003830038
1002430037225000612954725100101010000101000050427716013001830037300372828632876710010201000020100003003730037111002110910101000010000640216222962910000103003830038300383003830038
1002430037225000612954725100101010000101000050427716013001830037300372828632876710010201000020100003003730037111002110910101000010000640216222962910000103003830038300383003830038
1002430037225000612954725100101010000101000050427716003001830037300372828632876710010201000020100003003730037111002110910101000010000640216222962910000103003830038300383003830038
1002430037225000612954725100101010000101000050427716013001830037300372828632876710010201000020100003003730037111002110910101000010000640216222962910000103003830038300383003830038
1002430037224000612954725100101010000101000050427716013001830037300372828632876710010201000020100003003730037111002110910101000010000640216222962910000103003830038300383003830038
1002430037225000612954725100101010000101000050427716013001830037300372828632876710010201000020100003003730037111002110910101000010000640216222962910000103003830038300383003830038
1002430037225000612954725100101010000101000050427716013001830037300372828632876710010201000020100003003730037111002110910101000010000640216222962910000103003830038300383003830086
1002430037225000612954725100101010000101000050427716013001830037300372828632876710010201000020100003003730037111002110910101000010000640216222962910000103003830038300383003830038
1002430037225000612954725100101010000101000050427716013001830037300372828632876710010201000020100003003730037111002110910101000010200640216222962910000103003830038300383003830038

Test 3: throughput

Count: 8

Code:

  fcvtns h0, h8
  fcvtns h1, h8
  fcvtns h2, h8
  fcvtns h3, h8
  fcvtns h4, h8
  fcvtns h5, h8
  fcvtns h6, h8
  fcvtns h7, h8
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfmap dispatch bubble (d6)dde0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80204200391560302580108100800081008002050064013220020200392003999776999080120200800322008003220039200391180201100991001008000010000114180111511816020036800001002004020040200402004020040
80204200391550302580108100800081008002050064013220020200392003999776999080120200800322008003220039200391180201100991001008000010000130111511816020036800001002004020040200402004020040
802042003915506952580108100800081008002050064013220020200392003999776999080120200800322008003220039200391180201100991001008000010000100111511816020036800001002004020040200402004020040
80204200391560302580108100800081008002050064013220020200392003999776999080120200800322008003220039200391180201100991001008000010000300111511816020036800001002004020040200402004020040
80204200391553302580108100800081008002050064013220020200392003999776999080120200800322008003220039200391180201100991001008000010000030111511816020036800001002004020040200402004020040
802042003915503025801081008000810080020500640132200202003920039997769990801202008003220080032200392003911802011009910010080000100000390111511816020036800001002004020040200402004020040
80204200391559302580108100800081008002050064013220020200392003999776999080120200800322008003220039200391180201100991001008000010000000111511816020036800001002004020040200402004020040
802042003915503525801081008000810080020500640132200202003920039997769990801202008003220080032200392003911802011009910010080000100003600111511816020036800001002004020040200402004020040
80204200391560302580108100800081008002050064013220020200392003999776999080120200800322008003220039200391180201100991001008000010000500111511816020036800001002004020040200402004020040
80204200391550302580108100800081008002050064013220020200392003999776999080120200800322008003220039200391180201100991001008000010000500111511816020036800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03l2 tlb miss data (0b)18191e1f3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)6061696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd0d2d5map dispatch bubble (d6)dbddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8002420039155000000402580010108000010800005064000000200202003920039999631001980010208000020800002003920039118002110910108000010005020001316011112003680000102004020040200402004020040
80024200391550000004025800101080000108000050640000002002020039200399996310019800102080000208000020039200391180021109101080000100050205241601062003680000102004020040200402004020040
800242003915500030040258001010800001080000506400000020020200392003999963100198001020800002080000200392003911800211091010800001002750205210160572003680000102004020040200402004020040
80024200391550000004025800101080000108000050640000152002020039200399996310019800102080000208000020039200391180021109101080000100050205211160932003680000102004020040200402004020040
800242003915500030040258001010800001080000506400001520020200392003999963100198001020800002080000200392003911800211091010800001002015020536160762003680000102004020040200402004020040
8002420039156000000402580010108000010800005064000015200202003920039999631001980010208000020800002003920039118002110910108000010005020537160642003680000102004020040200402004020040
80024200391550000004025800101080000108000050640000002002020039200399996310019800102080000208000020039200391180021109101080000101050200051607132003680000102004020040200402004020040
800242003915500042006925800101080000108000050640000002002020039200399996310019800102080000208000020039200391180021109101080000100395020006160662003680000102004020040200402004020040
800242003915500012006825800101080000108000050640000002002020039200399996310019800102080000208000020039200391180021109101080000100050200041605112003680000102004020040200402004020040
8002420039161000000402580010108000010800005064000000200202003920039999631001980010208000020800002003920039118002110910108000010005020001016010102003680000102004020040200402004020040