Apple M1 Microarchitecture Research by Dougall Johnson

Firestorm: Overview | Base Instructions | SIMD and FP Instructions
Icestorm:  Overview | Base Instructions | SIMD and FP Instructions

FCVTNS (scalar, H to W)

Test 1: uops

Code:

  fcvtns w0, h0
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 3.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 2.000

retire (01)cycle (02)03071e3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch fp/simd (57)huge thing fp/simd (5b)696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op fp/simd (7e)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst integer (97)accfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
200454141043253000100020002000180005225415412483274200020002000541541111001100007511611538100010001000542542542542542
200454140357253000100020002000180005225415412483274200020002000541541111001100007311622538100010001000542542542542542
200454140043253000100020002000180005225415412483274200020002000541541111001100007311611538100010001000542542542542542
200454150043253000100020002000180005225415412483274200020002000541541111001100007311611538100010001000542542542542542
200454140043253000100020002000180005225415412483274200020002000541541111001100007521622538100010001000542542542542542
200454140043253000100020002000180005225415412483274200020002000541541111001100007521611538100010001000542542542542542
200454140043253000100020002000180005225415412483274200020002000541541111001100007311611538100010001000542542542542542
2004541501243253000100020002000180005225415412483274200020002000541541111001100007311611538100010001000542542542542542
200454140043253000100020002000180005225415412483274200020002000541541111001100007321622538100010001000542542542542542
200454141043253000100020002000180005225415412483274200020002000541541111001100007511611538100010001000542542542542542

Test 2: Latency 1->2 roundtrip

Code:

  fcvtns w0, h0
  fmov d0, x0
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 13.0038

retire (01)cycle (02)030b1e3f4f51inst issue (52)~issue int (53)~issue fp/simd (54)~issue ld/st (55)~dispatch int (56)~dispatch fp/simd (57)~dispatch ld/st (58)huge thing int (59)huge thing ld/st (5a)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op ld/st (7d)~map op fp/simd (7e)~map lookup int (7f)~map lookup ld/st (80)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa0a1a6a8accfd0d5d6ddinst fetch restart (de)e0? int output thing (e9)ld/st retires (ed)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
3020413003897400130023119417254010010100200001000010020000100005006214979148010341130013130038130038125476312624630100200100002000020010000200001300381300381120201100991001010010000100001000000131014163212952510000100001000010100130040130039130039130039130039
3020413003897400130023119417254010010100200001000010020000100005006214979148010341130013130038130038125476312624630100200100002000020010000200001300381300381120201100991001010010000100001001100131013163212952510000100001000010100130040130039130039130039130039
30204130038100900130023119417254010010100200001000010020000100005006214979148010341130013130038130038125476312624630100200100002000020010000200001300381300381120201100991001010010000100001000214383131013163312952510000100001000010100130046130039130039130039130039
3020413003897400130023119417254010010100200001000010020000100005006214979148010341130013130038130038125476312624830100200100002000020010000200001300381300381120201100991001010010000100001000030131013163212958110000100001000010100130039130039130039130039130039
3020413003897400130023119417254010010100200001000010020000100005006214979148010341130013130038130038125476312624630100200100002000020010000200001300381300381120201100991001010010000100001000000131012163212952510000100001000010100130039130039130077130087130039
3020413003897400130023119417254010010100200001000010020000100005006214979148010341130013130038130038125476312624630100200100002000020010000200001300381300381120201100991001010010000100001000000131013163312952510000100001000010100130039130039130039130039130039
3020413003897400130023119417254010010100200001000010020000100505006214979148010341130013130038130038125476312624630100200100002000020010000200001300381300381120201100991001010010000100221000000131013163312952510000100001000010100130039130039130039130039130039
3020413003897400130023119417384010010100200001000010020000100005006214979148010341130013130038130038125476312624630100200100002000020010000200001300381300381120201100991001010010000100001000000131013163312952510000100001000010100130041130039130039130039130039
3020413007697400130023119417254010010100200001000010020000100005006214979148010341130013130038130038125476312624630100200100002000020010000200001300381300381120201100991001010010000100001000000131013163312952510000100001000010100130039130039130039130039130039
3020413003897400130023119417254010010100200001000010020000100005006214979148010341130013130038130038125476312624630100200100002000020010000201321300791300391120201100991001010010000100001000000131013163312952510000100001000010100130039130039130039130039130039

1000 unrolls and 10 iterations

Result (median cycles for code): 13.0038

retire (01)cycle (02)031e1f3f4f51inst issue (52)~issue int (53)~issue fp/simd (54)~issue ld/st (55)~dispatch int (56)~dispatch fp/simd (57)~dispatch ld/st (58)huge thing int (59)huge thing ld/st (5a)huge thing fp/simd (5b)60696b6d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op ld/st (7d)~map op fp/simd (7e)~map lookup int (7f)~map lookup ld/st (80)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa1a6a8a9acc2c5branch mispredict (cb)cdcfd5d6ddinst fetch restart (de)e0? int output thing (e9)ld/st retires (ed)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
300241300389740013002311941725400101001020000100001020000100005062149791480002501300130130038130038125498312626830010201000020000201000020000130038130038112002110910100101000010010000000000012705162212952510000100001000010010130039130039130039130039130039
300241300389740013002311941725400101001020000100001220000100005062149791480002511300133130038130038125500312626530010201000020000201000020000130038130038112002110910100101000010010000000000012703161112952510000100001000010010130039130039130039130039130039
300241300389740013002311941725400101001020000100001020000100005062149791480002511300130130038130038125498312626830010201000020000201000020000130038130038112002110910100101000010010000100000012703162312952510000100001000010010130256130205130128130039130039
300241300389740013002311941725400101001020000100001020000100005062149791480002501300130130038130038125498312626830010201000020000201000020000130038130038112002110910100101000010010000000000012702163212952510000100001000010010130039130039130039130039130039
300241300389740013002311941725400101001020000100001020000100005062154451480002501300130130038130038125499312626830010201000020000201000020000130038130038112002110910100101000010010000000000012702162212952510000100001000010010130039130039130039130039130039
300241300389740013002311941725400101001020000100001020000100005062149791480002501300130130038130038125498312626830010201000020000201000020000130038130038112002110910100101000010010000000000012702161212952810000100001000010010130039130039130042130040130039
300241300389740013002311941725400101001020000100001020000100005062149791480002511300130130038130038125498312626830010201000020000201000020000130038130038112002110910100101000010010000000000012702162312952510000100001000010010130039130039130039130039130039
3002413003897400130023119417254001010010200001000010200001000050621497914800025113001301300381300381254983126268300102010000200002010000200001300381300381120021109101001010000100100008100000012702162312952510000100001000010010130039130039130039130039130039
300241300389740013002311941725400101001020000100001020000100005062149791480002511300130130038130038125498312626830010201000020000201000020000130038130038112002110910100101000010010000000000012702162312952510000100001000010010130039130039130039130039130042
3002413007310530013002311941725400101001020000100001020000100005062149791480002501300130130038130038125498312626830010201000020000201000020000130038130038112002110910100101000010010000000000012702162212952510000100001000010010130039130039130039130039130039

Test 3: throughput

Count: 8

Code:

  fcvtns w0, h8
  fcvtns w1, h8
  fcvtns w2, h8
  fcvtns w3, h8
  fcvtns w4, h8
  fcvtns w5, h8
  fcvtns w6, h8
  fcvtns w7, h8
  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

retire (01)cycle (02)0308181e1f3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)9fa8a9acc5branch mispredict (cb)cdcfd2d5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
1602044004130000003225240104801001600041001600205001440132400224004140041199776199921601202001600322001600324004140041118020110099100801001000001115117021600400388000080000801004004240042400424004240042
1602044004130000003225240104801001600041001600205001440132400224004140041199776199921601202001600322001600324004140041118020110099100801001000001115117001600400388000080000801004004240042400424004240042
16020440041300002703225240104801001600041001600205001440132400224004140041199776199921601202001600322001600324004140041118020110099100801001000001115117001600400388000080000801004004240042400424004240042
1602044004130000003225240104801001600041001600205001440132400224004140041199776199921601202001600322001600324004140041118020110099100801001000001115117001600400388000080000801004004240042400424004240042
1602044004130000003225240104801001600041001600205001440132400224004140041199776199921601202001600322001600324004140041118020110099100801001000001115117001600400388000080000801004004240042400424004240042
1602044004130000003225240104801001600041001600205001440132400224004140041199776199921601202001600322001600324004140041118020110099100801001000001115117001600400388000080000801004004240042400424004240042
1602044004130000003225240104801001600041001600205001440132400224004140041199776199921601202001600322001600324004140041118020110099100801001000001115117001600400388000080000801004004240042400424004240042
16020440041299000032252401048010016000410016002050014401324002240041400411997761999216012020016003220016003240041400411180201100991008010010000011151171801600400388000080000801004004240042400424004240042
1602044004130000003225240104801001600041001600205001440132400224004140041199776199921601202001600322001600324004140041118020110099100801001000001115117001604400388000080000801004004240042400424004240042
1602044004130000009525240104801001600041001600205001440132400224004140041199776199921601202001600322001600324004140041118020110099100801001000001115117001600400388000080000801004004240042400424004240042

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

retire (01)cycle (02)03051e3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)9fa0a8acc5branch mispredict (cb)cdcfd5d6d9ddinst fetch restart (de)e0? int output thing (e9)eaeb? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
160024400553100042252400108001016000010160000501440000140022400414004119996320021160010201600002016000040041400411180021109108001010000000502014160131140038800000080000800104004240042400424004240042
160024400413100042252400108001016000010160000501440000040022400414004119996320021160010201600002016000040041400411180021109108001010000000502013160121140038800000080000800104004240042400424004240042
160024400413100097252400108001016000010160000501440000040022400414004119996320021160010201600002016000040041400411180021109108001010400000502012160121340038800000080000800104004240042400424004240042
160024400413110042252400108001016000010160000501440000040022400414004119996320021160010201600002016000040041400411180021109108001010000000502012160111140038800000080000800104004240042400424004240042
160024400413110042252400108001016000010160000501440000040022400414004119996320021160010201600002016000040041400411180021109108001010000000502012160131340038800000080000800104004240042400424004240042
1600244004131000707252400108001016000010160000501440000040022400414004119996320021160010201600002016000040041400411180021109108001010000000502012160131140038800000080000800104004240042400424004240042
160024400413100042252400108001016000010160000501440000040022400414004119996320021160010201600002016000040041400411180021109108001010000000502010160111240038800000080000800104004240042400424004240042
160024400413100042252400108001016000010160000501440000040022400414004119996320021160010201600002016000040041400411180021109108001010000000502011160121240038800000080000800104004240042400424004240042
1600244004131000137252400108001016000010160000501440000140022400414004119996320021160010201600002016000040041400411180021109108001010000000502012160101140038800000080000800104004240042400424004240042
160024400413100042252400108001016000010160000501441862040022400414004119996320021160010201600002016000040041400411180021109108001010000000502015160121240038800000080000800104004240042400424004240042