Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FCVTNS (scalar, S to S)

Test 1: uops

Code:

  fcvtns s0, s0
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004303724061254725100010001000398160130183037303724143289510001000100030373037111001100000073116112629100030383038303830383038
10043037240612547251000100010003981601301830373037241432895100010001000303730371110011000051473116112629100030383038303830383038
1004303723061254725100010001000398160130183037303724143289510001000100030373037111001100000073116112629100030383038303830383038
1004303723061254725100010001000398160130183037303724143289510001000100030373037111001100010073116112629100030383038303830383038
1004303723661254725100010001000398160130183037303724143289510001000100030373037111001100003073116112629100030383038303830383038
1004303723061254725100010001000398160130183037303724143289510001000100030373037111001100000073116112629100030383038303830383038
1004303725061254725100010001000398160130183037303724143289510001000100030373037111001100000073116112629100030383038303830383038
1004303724061254725100010001000398160130183037303724143289510001000100030373037111001100000073116112629100030383038303830383038
1004303724061254725100010001000398160130183037303724143289510001000100030373037111001100000073116112629100030383038303830383038
1004303723061254725100010001000398160130183037303724143289510001000100030373037111001100000073116112629100030383038303830383038

Test 2: Latency 1->2

Code:

  fcvtns s0, s0
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)18191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043003723300002122954725101001001000010010000500427716003001830037300372826432874510100200100002001000030037300371110201100991001001000010000007101161129633100001003003830038300383003830038
102043003723300001502954725101001001000010010000500427716003001830037300372826432874510100200100002001000030037300371110201100991001001000010001007101161129633100001003003830038300383003830038
10204300372320000612954725101001001000010010000500427716003001830037300372826432874510100200100002001000030037300371110201100991001001000010000007101161129633100001003003830038300383003830038
10204300372330000612954725101001001000010010000500427716013001830037300372826432874510100200100002001000030037300371110201100991001001000010000007101161129633100001003003830038300383003830038
10204300372330000612954725101001001000010010000500427716013001830037300372826432874510100200100002001000030037300371110201100991001001000010000007101161129633100001003003830038300383003830038
102043003723300001872954725101001001000010010000500427716003001830037300372826432874510100200100002001000030037300371110201100991001001000010000007101161129633100001003003830038300383003830038
10204300372330000962954725101001001000010010000500427716003001830037300372826432874510100200100002001000030037300371110201100991001001000010000007101161129633100001003003830038300383003830038
102043003723200004812954725101001001000010010000500427716003001830037300372826432874510100200100002001000030037300371110201100991001001000010000007101161129633100001003003830038300383003830038
10204300372330000612954725101001001000010010000500427716003001830037300372826432874510100200100002001000030037300371110201100991001001000010000007101161129633100001003003830038300383003830038
10204300372330000612950925101001001000010010000500427716003001830037300372826432874510100200100002001000030037300371110201100991001001000010000007101161129633100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002430037224000001662954725100101010000101000050427716013001830037300372828632876710010201017920100003003730037111002110910101000010000006402162229629010000103003830038300383003830038
100243003722500000612954725100101010000101000050427716013001830037300372828632876710010201000020100003003730037111002110910101000010000006402162329629010000103003830038300383003830038
100243003722500000612954725100101010000101000050427716013001830037300372828632876710010201000020100003003730037111002110910101000010000006402162229629010000103003830038300383003830038
1002430037225000001662954725100101010000101000050427716003001830037300372828632876710010201000020100003003730037111002110910101000010000006402162329629010000103003830038300383003830038
100243003722500000612954725100101010000101000050427716013001830037300372828632876710010201000020100003003730037111002110910101000010000006402162329629010000103003830038300383003830038
100243003722500000612954725100101010000101000050427716003001830037300372828632876710010201000020100003003730037111002110910101000010000006402162329629010000103003830038300383003830038
100243003722500000612954725100101010000101000050427716013001830037300372828632876710010201000020100003003730037111002110910101000010000006402162229629010000103003830038300383003830038
100243003722500000612954725100101010000101000050427716013001830037300372828632876710010201000020100003003730037111002110910101000010000006402162329629010000103003830038300383003830038
100243003722500000612954725100101010000101000050427716003001830037300372828632876710010201000020100003003730037111002110910101000010000006402162329629010000103003830038300383003830038
100243003728400000612954744100101010000101000050427716013001830037300372828632876710010201000020100003003730037111002110910101000010000006402162229629010000103003830038300383003830038

Test 3: throughput

Count: 8

Code:

  fcvtns s0, s8
  fcvtns s1, s8
  fcvtns s2, s8
  fcvtns s3, s8
  fcvtns s4, s8
  fcvtns s5, s8
  fcvtns s6, s8
  fcvtns s7, s8
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0ea? simd retires (ee)? int retires (ef)f5f6f7f8fd
80204200391560302580108100800081008002050064013212002002003920039997769990801202008003220080032200392003911802011009910010080000100010111511801600200360800001002004020040200402004020040
80204200391560302580108100800081008002050064013202002002003920039997769990801202008003220080032200392003911802011009910010080000100000111511801600200360800001002004020040200402004020040
80204200391550302580108100800081008002050064013212002002003920039997769990801202008003220080032200392003911802011009910010080000100000111511801600200360800001002004020040200402004020040
80204200391550302580108100800081008002050064013212002002003920039997769990801202008003220080032200392003911802011009910010080000100000111511801600200360800001002004020040200402004020040
80204200391550302580108100800081008002050064013202002002003920039997769990801202008003220080032200392003911802011009910010080000100000111511811600200360800001002004020040200942004020090
80204201021550302580108100800081008002050064013212002002003920039997769990801202008003220080032200392003911802011009910010080000100000111511801600200360800001002004020040200402004020040
80204200391550302580108100800081008002050064013202002002003920039997769990801202008003220080032200392003911802011009910010080000100010111511801600200360800001002004020040200402004020040
80204200391550302580108100800081008002050064013212002002003920039997769990801202008003220080032200392003911802011009910010080000100000111511801600200360800001002004020040200402004020040
80204200391560302580108100800081008002050064013212002002003920039997769990801202008003220080032200392003911802011009910010080000100016111511801600200360800001002004020040200402004020040
80204200391560582580108100800081008002050064013212002002003920039997769990801202008003220080032200392003911802011009910010080000100010111511801600200360800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03l1i tlb fill (04)091e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)6061696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd0d2l1i cache miss demand (d3)l1i tlb miss demand (d4)d5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200391551108625800101080000108000050640000002002020039200399996310019800102080000208000020039200391180021109101080000100050385000248123232003680000102004020040200402004020040
8002420039155111212925800101080000108000050640000102002020039200399996310019800102080000208000020039200391180021109101080000100050210001133124222003680000102004020040200402004020040
800242003915511078225800101080000108000050640000052002020039200399996310019800102080000208000020039200391180021109101080000100050210001223022132003680000102004020040200402004020040
80024200391551108625800101080000108000050640000052002020039200399996310019800102080000208000020039200391180021109101080000100050210001223023182003680000102004020040200402004020040
80024200391551108625800101080000108012450640000002002020039200399996310019800102080000208000020039200391180021109101080000100050210001223123142003680000102004020040200402004020040
80024200391551108625800101080000108000050640000002002020039200399996310019800102080000208000020039200391180021109101080000100050210001183118222003680000102004020040200402004020040
80024200391551108625800101080000108000050640000002002020039200399996310019800102080000208000020039200391180021109101080000100050210101194617232003680000102004020040200402004020040
80024200391551108625800101080000108000050640000202002020039200399996310019800102080000208000020039200391180021109101080000101050200000331624152003680000102004020040200402004020040
80024200391550004025800101080000108000050640000002002020039200399996310019800102080000208000020039200391180021109101080000100050200000291623132003680000102004020040200402004020040
800242003915500124025800101080000108000050640000002002020039200399996310019800102080000208000020039200391180021109101080000100050200000321622232003680000102004020040200402004020040