Firestorm: FCVTNS (scalar, S to W) measurements

Code:

  fcvtns w0, s0

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 3.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 2.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	l1d cache writeback (a8)	a9	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	eb	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
2004	541	4	0	43	25	3000	1000	2000	2000	18000	0	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	73	2	16	2	2	538	1000	0	1000	1000	542	542	542	542	542
2004	541	4	0	43	25	3000	1000	2000	2000	18000	0	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	73	2	16	2	2	538	1000	0	1000	1000	542	542	542	542	542
2004	541	4	0	43	25	3000	1000	2000	2000	18000	0	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	73	2	16	2	2	538	1000	0	1000	1000	542	542	542	542	542
2004	541	4	0	43	25	3000	1000	2000	2000	18000	0	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	1	0	73	2	16	2	2	538	1000	0	1000	1000	542	542	542	542	542
2004	541	4	0	43	25	3000	1000	2000	2000	18000	0	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	73	2	16	2	2	538	1000	0	1000	1000	542	542	542	542	542
2004	541	5	0	43	25	3000	1000	2000	2000	18000	0	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	73	2	16	2	2	538	1000	0	1000	1000	542	542	542	542	542
2004	541	4	0	43	25	3000	1000	2000	2000	18000	0	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	73	2	16	2	2	538	1000	0	1000	1000	542	542	542	542	542
2004	541	4	0	43	25	3000	1000	2000	2000	18000	0	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	73	2	16	2	2	538	1000	0	1000	1000	542	542	542	542	542
2004	541	4	0	43	25	3000	1000	2000	2000	18000	0	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	1	0	73	2	16	2	2	538	1000	0	1000	1000	542	542	542	542	542
2004	541	4	0	43	25	3000	1000	2000	2000	18000	1	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	73	2	16	2	2	538	1000	0	1000	1000	542	542	542	542	542

Test 2: Latency 1->2 roundtrip

Code:

  fcvtns w0, s0
  fmov d0, x0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 13.0038

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30204	130038	974	0	0	0	0	0	0	0	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	0	130013	0	130038	130038	125476	3	126246	30100	200	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	0	0	1310	1	2	16	2	2	129525	10000	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	974	0	0	0	0	0	0	0	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	0	130013	0	130038	130038	125476	3	126246	30100	200	10000	20000	200	10000	20128	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	0	0	1310	1	2	16	2	2	129525	10000	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	974	0	0	0	0	0	0	0	0	130023	119462	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	0	130013	0	130054	130038	125476	3	126246	30100	200	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	0	0	1310	1	2	16	2	2	129525	10000	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	974	0	0	0	0	0	0	0	0	130023	119417	25	40100	10100	20003	10000	100	20000	10000	500	6214979	14801034	0	130013	0	130038	130038	125476	3	126246	30100	200	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	1	0	10000	0	5	0	16933	0	0	0	1310	1	2	16	2	2	129525	10000	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	974	0	0	0	0	0	9	0	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	0	130013	0	130038	130038	125476	3	126246	30100	200	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	0	0	1310	1	2	16	2	2	129525	10000	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	974	0	0	0	0	0	0	0	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	511	6214979	14801034	0	130013	0	130038	130039	125476	3	126247	30100	200	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	0	0	1310	1	2	16	2	2	129525	10000	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	974	0	0	0	0	0	9	0	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	0	130013	0	130038	130038	125476	3	126246	30100	200	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	0	0	1310	1	2	16	1	2	129525	10000	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	974	0	0	0	0	0	0	0	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	0	130013	0	130038	130038	125476	3	126246	30100	200	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	0	0	1310	1	2	16	2	2	129525	10000	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	974	0	0	0	0	0	0	0	0	130023	119421	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	0	130013	0	130038	130038	125476	3	126246	30100	200	10064	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	0	0	1310	1	2	16	2	2	129525	10000	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	974	0	0	0	0	0	0	0	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	0	130013	0	130038	130038	125476	3	126246	30100	200	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	0	0	1310	1	2	16	2	2	129528	10000	10000	10000	10100	130039	130039	130039	130039	130039

1000 unrolls and 10 iterations

Result (median cycles for code): 13.0038

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30024	130038	974	0	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6215075	14800025	0	130013	130038	130038	125498	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	0	1270	1	16	1	1	129525	10000	10000	10000	10010	130039	130039	130039	130039	130039
30024	130038	974	0	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6215075	14800025	0	130013	130038	130038	125552	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	0	1270	1	16	1	1	129525	10000	10000	10000	10010	130039	130039	130039	130039	130039
30024	130038	974	0	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6215027	14800025	0	130013	130038	130038	125498	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	0	1270	1	16	1	1	129525	10000	10000	10000	10010	130039	130039	130039	130039	130039
30024	130038	974	0	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6215123	14800025	0	130013	130038	130038	125498	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	0	1270	1	16	1	1	129527	10000	10000	10000	10010	130039	130039	130039	130039	130039
30024	130038	974	0	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	0	130013	130038	130038	125498	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	0	1270	1	16	1	1	129525	10000	10000	10000	10010	130039	130039	130039	130039	130039
30024	130038	974	0	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6215171	14800025	0	130013	130038	130038	125498	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	0	1270	1	16	2	1	129525	10000	10000	10000	10010	130039	130039	130039	130039	130039
30024	130044	974	0	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6215123	14800025	0	130013	130038	130038	125498	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	0	1270	1	16	1	1	129525	10000	10000	10000	10010	130039	130039	130039	130039	130039
30024	130038	974	3	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	0	130013	130038	130038	125498	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	0	0	10000	3	0	0	0	0	1270	1	16	1	1	129525	10000	10000	10000	10010	130039	130039	130039	130039	130043
30024	130038	974	0	130023	119417	25	40010	10010	20003	10000	10	20000	10000	50	6215219	14800025	1	130013	130038	130038	125498	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	0	1270	1	16	1	1	129525	10000	10000	10000	10010	130039	130039	130039	130039	130039
30024	130038	975	0	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	0	130013	130074	130041	125498	20	126318	30010	20	10000	20000	20	10000	20000	130038	130041	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	0	1270	1	16	1	1	129525	10000	10000	10000	10010	130039	130039	130039	130039	130039

Test 3: throughput

Count: 8

Code:

  fcvtns w0, s8
  fcvtns w1, s8
  fcvtns w2, s8
  fcvtns w3, s8
  fcvtns w4, s8
  fcvtns w5, s8
  fcvtns w6, s8
  fcvtns w7, s8

Initialization

  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5e	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	a9	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	map dispatch bubble (d6)	e0	? int output thing (e9)	eb	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	40041	322	0	0	0	0	0	0	0	0	32	25	240104	80100	160004	100	160020	500	1440132	0	0	40022	40041	40041	19977	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	1	1	1	5117	16	40038	80000	0	80000	80100	40042	40042	40042	40042	40042
160204	40041	310	0	0	0	0	0	0	0	0	32	25	240104	80100	160004	100	160020	500	1440132	0	0	40022	40041	40041	19977	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	1	1	1	5117	16	40038	80000	0	80000	80100	40042	40042	40042	40042	40042
160204	40041	310	0	0	0	0	0	12	0	0	32	25	240104	80100	160004	100	160020	500	1440132	0	0	40022	40041	40041	19977	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	1	1	1	5117	16	40038	80000	0	80000	80100	40042	40042	40042	40042	40042
160204	40041	310	0	0	0	0	0	0	0	0	32	25	240104	80100	160004	100	160020	500	1440132	0	0	40022	40041	40041	19977	6	19992	160308	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	1	1	1	5117	16	40038	80000	0	80000	80100	40042	40042	40042	40042	40042
160204	40041	310	0	0	0	0	0	0	0	0	32	25	240104	80100	160004	100	160020	500	1440132	0	0	40022	40041	40041	19977	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	1	1	1	5117	16	40038	80000	0	80000	80100	40042	40042	40042	40042	40042
160204	40041	310	0	0	0	1	0	0	0	0	127	25	240104	80100	160188	100	160020	500	1440132	0	0	40022	40041	40041	19977	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	1	1	1	5117	16	40038	80000	0	80000	80100	40042	40042	40042	40042	40042
160204	40041	313	1	0	1	14	12	1596	1056	0	5694	302	243561	81248	162572	104	162630	714	1460010	0	0	40795	40967	40200	20265	88	20579	162354	204	162470	206	162498	41079	41060	13	1	80201	100	99	100	80100	100	2	2	0	0	1	0	10093	1	1	1	5117	16	40038	80000	0	80000	80100	40042	40042	40042	40042	40042
160204	40041	310	0	0	0	9	10	1068	792	0	7605	192	243584	81334	162356	105	162458	558	1461840	0	0	40852	40978	40993	20293	96	20531	162592	204	162512	202	162056	41069	41083	14	1	80201	100	99	100	80100	100	0	0	0	1	0	0	0	1	1	1	5117	124	40874	81176	0	80000	80100	41159	41001	41001	40994	41001
160204	41221	321	0	0	0	14	14	2112	1408	0	4994	373	244824	81524	163068	108	163084	598	1468779	0	0	40981	41069	41315	20285	123	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	2	2	0	0	0	8125	1	1	1	5326	115	40557	81242	0	80000	80100	40771	40042	40042	40042	40042
160204	40041	311	0	0	1	0	0	924	264	1	7722	26	240116	80204	160012	100	160020	500	1440132	1	0	40022	40041	40041	19977	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	1	1	1	5117	16	40038	80000	0	80000	80100	40042	40042	40042	40042	40042

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	cf	d0	d5	map dispatch bubble (d6)	d9	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	40042	300	1	0	707	25	240010	80010	160000	10	160000	50	1440000	0	40022	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	5020	0	27	16	0	21	27	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	299	0	0	42	25	240010	80010	160000	10	160000	50	1440000	0	40022	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	5020	0	16	16	0	23	26	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	300	0	0	42	25	240010	80010	160000	10	160000	50	1440000	0	40022	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	5020	0	27	16	0	27	27	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	300	0	0	42	25	240010	80010	160000	10	160000	50	1440000	0	40022	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	5020	0	20	16	0	17	23	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	316	0	0	42	25	240010	80010	160000	10	160000	50	1440000	0	40022	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	1	0	5020	0	27	16	0	27	27	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	300	0	0	707	25	240010	80010	160000	10	160000	50	1440000	0	40022	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	5020	0	17	16	0	27	16	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	300	0	0	42	25	240010	80010	160000	10	160000	50	1440000	0	40022	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	5020	0	28	16	0	21	28	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	300	0	0	42	25	240010	80010	160000	10	160000	50	1440000	0	40022	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	5020	0	16	16	0	27	18	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	300	0	0	42	25	240290	80010	160000	10	160000	50	1440000	0	40022	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	5020	0	27	16	0	27	25	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	300	0	0	42	25	240010	80010	160000	10	160000	50	1440000	0	40022	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	5020	0	27	16	0	27	27	40038	80000	80000	80010	40042	40042	40042	40042	40042

FCVTNS (scalar, S to W)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations