Firestorm: FCVTNS (scalar, S to X) measurements

Code:

  fcvtns x0, s0

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 3.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 2.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	l1d cache writeback (a8)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
2004	541	4	0	43	25	3000	1000	2000	2000	18000	0	522	0	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	73	1	16	1	1	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	43	25	3000	1000	2000	2000	18000	0	522	0	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	73	1	16	1	1	538	1000	1000	1000	542	542	542	542	542
2004	541	5	0	43	25	3000	1000	2000	2000	18000	0	522	0	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	73	1	16	1	1	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	64	25	3000	1000	2000	2000	18000	0	522	0	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	73	1	16	1	1	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	43	25	3000	1000	2000	2000	18000	0	522	0	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	73	1	16	1	1	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	43	25	3000	1000	2000	2000	18000	0	522	0	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	73	1	16	1	1	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	43	25	3000	1000	2000	2000	18000	0	522	0	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	73	1	16	1	1	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	43	25	3000	1000	2000	2000	18000	0	522	0	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	73	1	16	1	1	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	43	25	3000	1000	2000	2000	18000	0	522	0	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	73	1	16	1	1	538	1000	1000	1000	542	542	542	542	542
2004	541	4	12	85	25	3000	1000	2000	2000	18000	0	522	0	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	73	1	16	1	1	538	1000	1000	1000	542	542	542	542	542

Test 2: Latency 1->2 roundtrip

Code:

  fcvtns x0, s0
  fmov d0, x0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 13.0038

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	18	19	1e	1f	3a	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	ld unit uop (a6)	st unit uop (a7)	l1d cache writeback (a8)	ac	c2	branch cond mispred nonspec (c5)	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30204	130038	974	0	0	0	30	0	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	1	130013	130038	130038	125476	3	126246	30100	200	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	10000	0	1	0	0	0	0	1310	1	3	16	2	2	129525	10000	10000	10000	10100	130042	130075	130074	130045	130039
30204	130038	974	0	0	0	0	0	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	1	130013	130038	130038	125476	3	126246	30100	200	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	0	0	1310	1	2	16	2	3	129525	10000	10000	10000	10100	130044	130039	130039	130039	130039
30204	130038	974	0	0	0	0	0	0	130024	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14802747	1	130017	130038	130038	125476	3	126246	30100	200	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	0	0	1310	1	3	16	3	3	129525	10000	10000	10000	10100	130040	130039	130039	130039	130039
30204	130038	974	0	0	0	0	0	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	1	130013	130038	130038	125476	3	126246	30100	200	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	0	0	1310	1	2	16	2	2	129525	10000	10000	10000	10100	130041	130039	130039	130039	130039
30204	130038	974	0	0	0	9	0	0	130023	119417	25	40100	10105	20000	10000	100	20000	10000	500	6214979	14801034	1	130013	130038	130038	125476	3	126246	30100	200	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	0	0	1310	1	2	16	3	2	129525	10000	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	974	0	0	0	12	0	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	1	130019	130038	130038	125479	3	126249	30100	200	10000	20000	200	10000	20000	130038	130039	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	0	0	1310	1	3	16	3	3	129525	10000	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	974	0	0	0	0	0	0	130083	119417	25	40143	10100	20006	10004	108	20000	10049	577	6219121	14821096	1	130013	130038	130040	125476	3	126246	30100	200	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	3	0	0	0	1310	1	2	16	2	2	129525	10000	10000	10000	10100	130062	130039	130039	130039	130039
30204	130038	973	0	0	0	0	0	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	1	130013	130038	130038	125476	3	126246	30100	200	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	0	0	1310	1	2	16	2	2	129525	10000	10000	10000	10100	130039	130039	130039	130072	130039
30204	130038	974	0	0	0	0	0	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	1	130013	130038	130038	125476	3	126246	30100	200	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	10000	0	4	0	0	0	0	1310	1	3	16	3	3	129525	10000	10000	10000	10100	130061	130040	130039	130039	130039
30204	130038	974	0	0	0	0	0	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	1	130013	130042	130038	125479	3	126246	30100	200	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	0	0	1310	1	2	16	3	3	129525	10000	10000	10000	10100	130088	130042	130039	130039	130039

1000 unrolls and 10 iterations

Result (median cycles for code): 13.0038

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	19	1e	1f	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30024	130038	974	0	0	0	0	0	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	1	130023	3	130038	130038	125498	3	126268	30010	20	10000	20000	20	10000	20000	130040	130038	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	0	0	1270	2	16	6	1	129525	10003	10000	10000	10010	130039	130039	130458	130128	130039
30024	130038	977	0	0	0	897	0	130023	119417	25	40010	10010	20000	10001	10	20000	10000	50	6215027	14800025	1	130031	0	130038	130038	125498	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	0	0	1270	1	16	1	1	129525	10000	10000	10000	10010	130039	130039	130039	130039	130039
30024	130038	974	0	0	0	15	0	130024	119417	25	40010	10010	20000	10000	10	20000	10000	50	6215123	14800025	1	130037	0	130041	130038	125498	3	126268	30010	20	10000	20000	20	10000	20123	130038	130038	1	1	20021	10	9	10	10010	10000	10	0	10000	1	0	0	0	0	1270	1	16	1	1	129525	10000	10000	10000	10010	130039	130039	130039	130039	130039
30024	130121	974	0	0	0	15	0	130023	119417	25	40010	10010	20000	10000	12	20000	10000	50	6214979	14800025	1	130036	0	130040	130038	125498	3	126269	30177	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	0	10000	1	2	0	0	0	1289	1	16	1	2	129525	10000	10000	10000	10010	130549	132686	132679	132821	132795
30024	130038	974	1	36	35	4764	3168	133418	120792	888	40239	10055	20128	10071	16	24179	12009	77	6312300	14984649	1	132744	0	132402	132309	126469	3	126268	30010	22	11988	24002	20	12087	23754	132746	132661	33	1	20021	10	9	10	10010	10000	10	0	10065	1	0	145708	6	0	1844	5	284	2	1	129525	10028	10000	10000	10010	130046	130040	130039	130039	132276
30024	132433	990	0	28	26	3831	2464	132583	120321	549	40188	10046	20079	10048	15	23700	11274	83	6273269	14944022	1	130025	0	130038	130038	125544	3	126318	30010	20	10000	20007	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	0	0	1270	1	16	1	1	129525	10000	10000	10000	10010	130039	130039	130039	130039	130039
30024	130038	974	0	0	0	0	0	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6215445	14800025	1	130017	0	130038	130038	125498	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	0	0	1270	1	16	1	1	129525	10000	10000	10000	10010	130039	130040	130039	130039	130039
30024	130038	1008	0	0	0	0	108	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	0	130043	0	130038	130038	125498	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	2	1	20021	10	9	10	10010	10000	10	0	10000	4	0	0	0	0	1270	1	16	1	1	129525	10000	10000	10000	10010	130039	130039	130039	130039	130039
30024	130038	974	0	0	0	0	0	130023	119417	25	40010	10012	20000	10000	10	20000	10000	50	6214979	14800025	0	130015	0	130081	130041	125498	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	0	0	1270	1	16	1	1	129525	10000	10000	10000	10010	130039	130039	130039	130039	130039
30024	130038	974	0	0	0	0	0	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	1	130014	0	130038	130038	125498	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	0	0	1270	1	16	1	1	129525	10000	10000	10000	10010	130039	130039	130039	130062	130039

Test 3: throughput

Count: 8

Code:

  fcvtns x0, s8
  fcvtns x1, s8
  fcvtns x2, s8
  fcvtns x3, s8
  fcvtns x4, s8
  fcvtns x5, s8
  fcvtns x6, s8
  fcvtns x7, s8

Initialization

  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	rob full (74)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	40062	310	0	0	0	0	32	25	240104	80100	160004	100	160020	500	1440132	0	40022	40041	40041	19977	0	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	1	1	1	5117	1	16	0	40038	80000	80000	80100	40042	40042	40042	40042	40042
160204	40041	310	0	0	0	0	32	25	240104	80100	160004	100	160020	500	1440132	0	40022	40041	40041	19977	0	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	1	1	1	5117	0	16	0	40038	80000	80000	80100	40042	40042	40042	40042	40042
160204	40041	310	0	0	0	0	32	25	240104	80100	160004	100	160020	500	1440132	0	40022	40041	40041	19977	0	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	1	1	1	5117	0	16	0	40038	80000	80000	80100	40042	40042	40042	40042	40042
160204	40041	311	0	0	0	0	32	25	240104	80100	160004	100	160020	500	1440132	1	40022	40041	40041	19977	0	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	1	1	1	5117	0	16	0	40038	80000	80000	80100	40042	40042	40042	40042	40042
160204	40041	310	0	0	0	0	32	25	240104	80100	160004	100	160020	500	1440132	1	40022	40041	40041	19977	0	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	1	1	1	5117	0	16	0	40038	80000	80000	80100	40042	40042	40042	40042	40042
160204	40041	310	0	0	0	0	32	25	240104	80100	160004	100	160020	500	1440132	1	40022	40041	40041	19977	0	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	1	1	1	5117	0	16	0	40038	80000	80000	80100	40042	40042	40042	40042	40042
160204	40041	310	0	0	0	0	697	25	240104	80100	160004	100	160020	500	1440132	1	40022	40041	40041	19977	0	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	1	0	1	1	1	5117	0	16	0	40038	80000	80000	80100	40042	40042	40042	40042	40042
160204	40041	310	0	0	0	0	32	25	240104	80100	160004	100	160020	500	1440132	1	40022	40041	40041	19977	0	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	1	1	1	5117	0	16	0	40038	80000	80000	80100	40042	40042	40042	40042	40042
160204	40041	310	0	0	0	0	32	25	240104	80100	160004	100	160020	500	1440132	0	40022	40041	40041	19977	0	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	1	1	1	5117	0	16	0	40038	80000	80000	80100	40042	40042	40042	40042	40042
160204	40041	310	0	0	0	0	32	25	240104	80100	160004	100	160020	500	1440132	0	40022	40041	40041	19977	0	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	1	1	1	5117	0	16	0	40038	80000	80000	80100	40042	40042	40042	40042	40042

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9e	9f	l1d cache writeback (a8)	a9	ac	branch mispred nonspec (cb)	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	dd	fetch restart (de)	df	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	40054	310	0	130	25	240010	80010	160000	10	160000	50	1440000	0	40022	0	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	0	10	0	0	0	0	5025	0	0	0	6	16	4	4	4	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	310	0	42	25	240010	80010	160000	10	160000	50	1440000	0	40022	0	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	0	10	0	0	0	0	5025	0	0	0	2	16	6	2	5	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	327	0	42	25	240010	80010	160000	10	160000	50	1440000	0	40022	0	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	0	10	0	0	0	0	5024	0	0	0	7	16	2	4	4	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	310	0	42	25	240010	80010	160000	10	160000	50	1440000	0	40022	0	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	0	10	0	0	0	0	5024	0	0	0	4	16	6	4	5	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	311	0	42	25	240010	80010	160000	10	160000	50	1440000	0	40022	0	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	0	10	0	0	0	0	5024	0	0	0	7	16	4	2	5	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	310	0	70	25	240010	80010	160200	10	160000	50	1440000	0	40022	0	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	0	10	0	0	0	0	5024	0	0	0	2	16	4	4	4	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	310	0	707	25	240010	80010	160000	10	160000	50	1440000	0	40022	0	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	0	10	0	0	0	0	5024	0	0	0	4	16	4	2	4	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	310	12	42	25	240010	80010	160000	10	160000	50	1440000	1	40022	0	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	0	10	0	0	0	0	5024	0	0	0	2	16	4	2	4	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	310	0	42	25	240010	80010	160000	10	160000	50	1440000	1	40022	0	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	0	10	0	0	0	0	5024	0	0	0	4	16	4	4	4	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	310	0	42	25	240010	80010	160000	10	160024	50	1440000	0	40022	0	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	0	10	0	0	0	0	5024	3	0	0	4	16	4	8	5	40038	80000	80000	80010	40042	40042	40042	40042	40042

FCVTNS (scalar, S to X)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations