Apple M1 Microarchitecture Research by Dougall Johnson

Firestorm: Overview | Base Instructions | SIMD and FP Instructions
Icestorm:  Overview | Base Instructions | SIMD and FP Instructions

FCVTNS (scalar, S to X)

Test 1: uops

Code:

  fcvtns x0, s0
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 3.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 2.000

retire (01)cycle (02)031e3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch fp/simd (57)huge thing fp/simd (5b)60696b6d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op fp/simd (7e)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst integer (97)a8cfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
2004541404325300010002000200018000052205415412483274200020002000541541111001100007311611538100010001000542542542542542
2004541404325300010002000200018000052205415412483274200020002000541541111001100007311611538100010001000542542542542542
2004541504325300010002000200018000052205415412483274200020002000541541111001100007311611538100010001000542542542542542
2004541406425300010002000200018000052205415412483274200020002000541541111001100007311611538100010001000542542542542542
2004541404325300010002000200018000052205415412483274200020002000541541111001100007311611538100010001000542542542542542
2004541404325300010002000200018000052205415412483274200020002000541541111001100007311611538100010001000542542542542542
2004541404325300010002000200018000052205415412483274200020002000541541111001100007311611538100010001000542542542542542
2004541404325300010002000200018000052205415412483274200020002000541541111001100007311611538100010001000542542542542542
2004541404325300010002000200018000052205415412483274200020002000541541111001100007311611538100010001000542542542542542
20045414128525300010002000200018000052205415412483274200020002000541541111001100007311611538100010001000542542542542542

Test 2: Latency 1->2 roundtrip

Code:

  fcvtns x0, s0
  fmov d0, x0
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 13.0038

retire (01)cycle (02)030818191e1f3a3f4f51inst issue (52)~issue int (53)~issue fp/simd (54)~issue ld/st (55)~dispatch int (56)~dispatch fp/simd (57)~dispatch ld/st (58)huge thing int (59)huge thing ld/st (5a)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op ld/st (7d)~map op fp/simd (7e)~map lookup int (7f)~map lookup ld/st (80)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa0a6a7a8acc2c5cdcfd0d5d6ddinst fetch restart (de)e0? int output thing (e9)ld/st retires (ed)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
302041300389740003000130023119417254010010100200001000010020000100005006214979148010341130013130038130038125476312624630100200100002000020010000200001300381300381120201100991001010010000100010000010000131013162212952510000100001000010100130042130075130074130045130039
30204130038974000000130023119417254010010100200001000010020000100005006214979148010341130013130038130038125476312624630100200100002000020010000200001300381300381120201100991001010010000100010000000000131012162312952510000100001000010100130044130039130039130039130039
30204130038974000000130024119417254010010100200001000010020000100005006214979148027471130017130038130038125476312624630100200100002000020010000200001300381300381120201100991001010010000100010000000000131013163312952510000100001000010100130040130039130039130039130039
30204130038974000000130023119417254010010100200001000010020000100005006214979148010341130013130038130038125476312624630100200100002000020010000200001300381300381120201100991001010010000100010000000000131012162212952510000100001000010100130041130039130039130039130039
30204130038974000900130023119417254010010105200001000010020000100005006214979148010341130013130038130038125476312624630100200100002000020010000200001300381300381120201100991001010010000100010000000000131012163212952510000100001000010100130039130039130039130039130039
302041300389740001200130023119417254010010100200001000010020000100005006214979148010341130019130038130038125479312624930100200100002000020010000200001300381300391120201100991001010010000100010000000000131013163312952510000100001000010100130039130039130039130039130039
30204130038974000000130083119417254014310100200061000410820000100495776219121148210961130013130038130040125476312624630100200100002000020010000200001300381300381120201100991001010010000100010000003000131012162212952510000100001000010100130062130039130039130039130039
30204130038973000000130023119417254010010100200001000010020000100005006214979148010341130013130038130038125476312624630100200100002000020010000200001300381300381120201100991001010010000100010000000000131012162212952510000100001000010100130039130039130039130072130039
30204130038974000000130023119417254010010100200001000010020000100005006214979148010341130013130038130038125476312624630100200100002000020010000200001300381300381120201100991001010010000100010000040000131013163312952510000100001000010100130061130040130039130039130039
30204130038974000000130023119417254010010100200001000010020000100005006214979148010341130013130042130038125479312624630100200100002000020010000200001300381300381120201100991001010010000100010000000000131012163312952510000100001000010100130088130042130039130039130039

1000 unrolls and 10 iterations

Result (median cycles for code): 13.0038

retire (01)cycle (02)030b18191e1f3f4f51inst issue (52)~issue int (53)~issue fp/simd (54)~issue ld/st (55)~dispatch int (56)~dispatch fp/simd (57)~dispatch ld/st (58)huge thing int (59)huge thing ld/st (5a)huge thing fp/simd (5b)60696b6d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op ld/st (7d)~map op fp/simd (7e)~map lookup int (7f)~map lookup ld/st (80)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa0a6a8a9acc2cdcfd5d6ddinst fetch restart (de)e0? int output thing (e9)ld/st retires (ed)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
3002413003897400000130023119417254001010010200001000010200001000050621497914800025113002331300381300381254983126268300102010000200002010000200001300401300381120021109101001010000100100000000012702166112952510003100001000010010130039130039130458130128130039
300241300389770008970130023119417254001010010200001000110200001000050621502714800025113003101300381300381254983126268300102010000200002010000200001300381300381120021109101001010000100100000000012701161112952510000100001000010010130039130039130039130039130039
30024130038974000150130024119417254001010010200001000010200001000050621512314800025113003701300411300381254983126268300102010000200002010000201231300381300381120021109101001010000100100001000012701161112952510000100001000010010130039130039130039130039130039
30024130121974000150130023119417254001010010200001000012200001000050621497914800025113003601300401300381254983126269301772010000200002010000200001300381300381120021109101001010000100100001200012891161212952510000100001000010010130549132686132679132821132795
30024130038974136354764316813341812079288840239100552012810071162417912009776312300149846491132744013240213230912646931262683001022119882400220120872375413274613266133120021109101001010000100100651014570860184452842112952510028100001000010010130046130040130039130039132276
3002413243399002826383124641325831203215494018810046200791004815237001127483627326914944022113002501300381300381255443126318300102010000200072010000200001300381300381120021109101001010000100100000000012701161112952510000100001000010010130039130039130039130039130039
3002413003897400000130023119417254001010010200001000010200001000050621544514800025113001701300381300381254983126268300102010000200002010000200001300381300381120021109101001010000100100000000012701161112952510000100001000010010130039130040130039130039130039
3002413003810080000108130023119417254001010010200001000010200001000050621497914800025013004301300381300381254983126268300102010000200002010000200001300381300382120021109101001010000100100004000012701161112952510000100001000010010130039130039130039130039130039
3002413003897400000130023119417254001010012200001000010200001000050621497914800025013001501300811300411254983126268300102010000200002010000200001300381300381120021109101001010000100100000000012701161112952510000100001000010010130039130039130039130039130039
3002413003897400000130023119417254001010010200001000010200001000050621497914800025113001401300381300381254983126268300102010000200002010000200001300381300381120021109101001010000100100000000012701161112952510000100001000010010130039130039130039130062130039

Test 3: throughput

Count: 8

Code:

  fcvtns x0, s8
  fcvtns x1, s8
  fcvtns x2, s8
  fcvtns x3, s8
  fcvtns x4, s8
  fcvtns x5, s8
  fcvtns x6, s8
  fcvtns x7, s8
  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

retire (01)cycle (02)03080b1e1f3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696d6edispatch stall (70)74scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)9fa8acc5branch mispredict (cb)cdcfd5d6dde0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
160204400623100000322524010480100160004100160020500144013204002240041400411997706199921601202001600322001600324004140041118020110099100801001000011151171160400388000080000801004004240042400424004240042
160204400413100000322524010480100160004100160020500144013204002240041400411997706199921601202001600322001600324004140041118020110099100801001000011151170160400388000080000801004004240042400424004240042
160204400413100000322524010480100160004100160020500144013204002240041400411997706199921601202001600322001600324004140041118020110099100801001000011151170160400388000080000801004004240042400424004240042
160204400413110000322524010480100160004100160020500144013214002240041400411997706199921601202001600322001600324004140041118020110099100801001000011151170160400388000080000801004004240042400424004240042
160204400413100000322524010480100160004100160020500144013214002240041400411997706199921601202001600322001600324004140041118020110099100801001000011151170160400388000080000801004004240042400424004240042
160204400413100000322524010480100160004100160020500144013214002240041400411997706199921601202001600322001600324004140041118020110099100801001000011151170160400388000080000801004004240042400424004240042
1602044004131000006972524010480100160004100160020500144013214002240041400411997706199921601202001600322001600324004140041118020110099100801001001011151170160400388000080000801004004240042400424004240042
160204400413100000322524010480100160004100160020500144013214002240041400411997706199921601202001600322001600324004140041118020110099100801001000011151170160400388000080000801004004240042400424004240042
160204400413100000322524010480100160004100160020500144013204002240041400411997706199921601202001600322001600324004140041118020110099100801001000011151170160400388000080000801004004240042400424004240042
160204400413100000322524010480100160004100160020500144013204002240041400411997706199921601202001600322001600324004140041118020110099100801001000011151170160400388000080000801004004240042400424004240042

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

retire (01)cycle (02)031e3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696b6d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)9e9fa8a9acbranch mispredict (cb)cfd0d2icache miss (d3)d5d6ddinst fetch restart (de)dfe0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
1600244005431001302524001080010160000101600005014400000400220400414004119996320021160010201600002016000040041400411180021109108001001000005025000616444400388000080000800104004240042400424004240042
160024400413100422524001080010160000101600005014400000400220400414004119996320021160010201600002016000040041400411180021109108001001000005025000216625400388000080000800104004240042400424004240042
160024400413270422524001080010160000101600005014400000400220400414004119996320021160010201600002016000040041400411180021109108001001000005024000716244400388000080000800104004240042400424004240042
160024400413100422524001080010160000101600005014400000400220400414004119996320021160010201600002016000040041400411180021109108001001000005024000416645400388000080000800104004240042400424004240042
160024400413110422524001080010160000101600005014400000400220400414004119996320021160010201600002016000040041400411180021109108001001000005024000716425400388000080000800104004240042400424004240042
160024400413100702524001080010160200101600005014400000400220400414004119996320021160010201600002016000040041400411180021109108001001000005024000216444400388000080000800104004240042400424004240042
1600244004131007072524001080010160000101600005014400000400220400414004119996320021160010201600002016000040041400411180021109108001001000005024000416424400388000080000800104004240042400424004240042
1600244004131012422524001080010160000101600005014400001400220400414004119996320021160010201600002016000040041400411180021109108001001000005024000216424400388000080000800104004240042400424004240042
160024400413100422524001080010160000101600005014400001400220400414004119996320021160010201600002016000040041400411180021109108001001000005024000416444400388000080000800104004240042400424004240042
160024400413100422524001080010160000101600245014400000400220400414004119996320021160010201600002016000040041400411180021109108001001000005024300416485400388000080000800104004240042400424004240042