Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FCVTNS (vector, 4H)

Test 1: uops

Code:

  fcvtns v0.4h, v0.4h
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004303724156125472510001000100039816013018303730372414328951000100010003037303711100110001073216222629100030383038303830383038
100430372306125472510001000100039816013018303730372414328951000100010003037303711100110000073216222629100030383038303830383038
100430372406125472510001000100039816013018303730372414328951000100010003037303711100110000073216222629100030383038303830383038
1004303724216125472510001000100039816013018303730372414328951000100010003037303711100110000073216222629100030383038303830383038
100430372406125472510001000100039816013018303730372414328951000100010003037303711100110000073216222629100030383038303830383038
100430372396125472510001000100039816013018303730372414328951000100010003037303711100110000073216222629100030383038303830383038
10043037231284254725100010001000398160130183037303724143289510001000100030373037111001100002473216222629100030383038303830383038
100430372406125472510001000100039816013018303730372414328951000100010003037303711100110000073216222629100030383038303830383038
100430372306125472510001000100039816013018303730372414328951000100010003037303711100110000073216222629100030383038303830383038
100430372306125472510001000100039816013018303730372414328951000100010003037303711100110000073216222629100030383038303830383038

Test 2: Latency 1->2

Code:

  fcvtns v0.4h, v0.4h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)a9acbranch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0ea? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020430037233084295472510100100100001001000050042771600300183003730037282643287451010020410000200100003003730037111020110099100100100001000000071011611296330100001003003830038300383003830038
1020430037232061295472510100100100001001000050042771600300183003730037282643287451010020010000200100003003730037111020110099100100100001000000071011611296330100001003003830038300383003830038
1020430037233061295472510100100100001001000050042771601300183003730037282643287451010020010000200100003003730037111020110099100100100001000000071011611296330100001003003830038300383003830038
1020430037233061295472510100100100001001000050042771601300183003730037282643287451010020010000200100003003730037111020110099100100100001000000071011611296330100001003003830038300383003830038
10204300372330673295472510100100100001001000050042771601300183003730037282643287451010020010000200100003003730037111020110099100100100001000000071011611296330100001003003830038300383003830038
1020430037232961295472510100100100001001000050042771600300183003730037282648287451010020010000200100003003730037111020110099100100100001000000071011611296330100001003003830038300383003830038
1020430037233061295472510100100100001001000050042771600300183003730037282643287451010020010000200100003003730037111020110099100100100001000000071011611296330100001003003830038300383003830038
10204300372330253295472510100100100001001000050042771600300183003730037282643287451010020010000200100003003730037111020110099100100100001000000071011611296330100001003003830038300383003830038
1020430037233061295472510100100100001001000050042771600300183003730037282643287451010020010000200100003003730037111020110099100100100001000000071011611296330100001003003830038300383003830038
1020430037232061295472510100100100001001000050042771600300183003730037282643287451010020010000200100003003730037111020110099100100100001000000071011611296330100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002430037225015629547251001010100001010000504277160300183003730037282863287671001020100002010000300373003711100211091010100001000640416662962910000103003830038300383003830038
100243003722506129547251001010100001010000504277160300183003730037282863287671001020100002010000300373003711100211091010100001000640616662962910000103003830038300383003830038
100243003722506129547251001010100001010000504277160300183003730037282863287671001020100002010000300373003711100211091010100001000640416552962910000103003830038300383003830038
100243003723306129547251001010100001010000504277160300183003730037282863287671001020100002010000300373003711100211091010100001000640416552962910000103003830038300383003830038
100243003722506129547251001010100001010000504277160300183003730037282863287671001020100002010000300373003711100211091010100001040640516652962910000103003830038300383003830038
1002430037225053629547251001010100001010000504277160300183003730037282863287671001020100002010000300373003711100211091010100001000640516652962910000103003830038300383003830038
10024300372250612954725100101010000101000050427716030018300373003728286328767100102010000201000030037300371110021109101010000100168640616662962910000103003830038300383003830038
1002430037225072629547251001010100001010000504277160300183003730037282863287671001020100002010000300373003711100211091010100001000640516552962910000103008130038300383003830038
1002430037224034929547251001010100001010000504277160300183003730037282863287671001020100002010000300373003711100211091010100001000640516552962910000103003830038300383003830038
100243003722506129547251001010100001010000504277160300183003730037282863287671001020100002010000300373003711100211091010100001000640516552962910000103003830038300383003830038

Test 3: throughput

Count: 8

Code:

  fcvtns v0.4h, v8.4h
  fcvtns v1.4h, v8.4h
  fcvtns v2.4h, v8.4h
  fcvtns v3.4h, v8.4h
  fcvtns v4.4h, v8.4h
  fcvtns v5.4h, v8.4h
  fcvtns v6.4h, v8.4h
  fcvtns v7.4h, v8.4h
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)030e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80204200611550847258010810080008100800205006401320200200200392003999776999080120200800322008003220039200391180201100991001008000010000011151180160020036800001002004020040200402004020040
80204200391550252258010810080008100800205006401320200200200392003999776999080120200800322008003220039200391180201100991001008000010000011151180160020036800001002004020040200402004020040
80204200391550114258010810080008100800205006401320200200200392003999776999080120200800322008003220039200391180201100991001008000010000011151180160020036800001002004020040200402004020040
80204200391550779258010810080008100800205006401320200200200392003999776999080120200800322008003220039200391180201100991001008000010000011151180160020036800001002004020040200402004020040
8020420039155051258010810080008100800205006401320200200200392003999776999080120200800322008003220039200391180201100991001008000010001011151180160020036800001002004020040200402004020040
80204200391560202258010810080008100800205006401320200200200392003999776999080120200800322008003220039200391180201100991001008000010000011151180160020036800001002004020040200402004020040
80204200391550179258010810080008100800205006401320200200200392003999776999080120200800322008003220039200391180201100991001008000010000011151180160020036800001002004020040200402004020040
8020420039155030258010810080008100800205006401320200200200392003999776999080120200800322008003220039200391180201100991001008000010022311151180160020036800001002004020040200402004020040
80204200391560572258010810080008100800205006401320200200200392003999776999080120200800322008003220039200391180201100991001008000010000011151180160020036800001002004020040200402004020040
8020420039155095258010810080008100800205006401320200200200392003999776999080120200800322008003220039200391180201100991001008000010000011151180160020036800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03181e1f3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0eaeb? simd retires (ee)? int retires (ef)f5f6f7f8fd
800242003916700024125800101080000108000050640000020020200392003999963100198001020800002080000200392003911800211091010800001000502415162015200360080000102004020040200402004020040
800242003915500024125800101080000108000050640000120020200392003999963100198001020800002080000200392003911800211091010800001000502414161513200360080000102004020040200402004020040
800242003915500024125800101080000108000050640000120020200392003999963100198001020800002080000200392003911800211091010800001000502415161315200360080000102004020040200402004020040
800242003915600024125800101080000108000050640000120020200392003999963100198001020800002080000200392007511800211091010800001000502418161315200360080000102004020040200402004020040
800242003915500024125800101080000108000050640000120020200392003999963100198001020800002080000200392003911800211091010800001000502415161515200360080000102004020040200402004020040
800242003915500024625800101080000108000050640000120020200392003999963100198001020800002080000200392003911800211091010800001000502415161415200360080000102004020040200402004020040
800242003915500024125800101080000108000050640000120020200392003999963100198001020800002080000200392003911800211091010800001000502412161513200360080000102004020040200402004020040
800242003915500021272580010108000010800005064000012002020039200399996310019800102080000208000020039200391180021109101080000100050241416817200360080000102004020040200402004020040
80024200391550002412580010108000010800005064000002002020039200399996310019800102080000208000020039200391180021109101080000100050241316915200360080000102004020040200402004020040
800242003915500024125800101080000108000050640000020020200392003999963100198001020800002080000200392003911800211091010800001000502416161416200360080000102004020040200402004020040