Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FCVTNS (vector, 8H)

Test 1: uops

Code:

  fcvtns v0.8h, v0.8h
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)6061696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd0d2d5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100430372306125472510001000100039816010301830373037241432895100010001000303730371110011000007300116112629100030383038303830383038
1004303724012425472510001000100039816000301830373037241432895100010001000303730371110011000007300116112629100030383038303830383038
1004303723022025472510001000100039816000301830373037241432895100010001000303730371110011000207300116112629100030383038303830383038
1004303723010325472510001000100039816000301830373037241432895100010001000303730371110011000237300116112629100030383038303830383038
1004303724031425472510001000100039816000301830373037241432895100010001000303730371110011000007300116112629100030383038303830383038
100430372406125472510001000100039816000301830373037241432895100010001000303730371110011000107300116112629100030383038303830383038
100430372406125472510001000100039816000301830373037241432895100010001000303730371110011000107300116112629100030383038303830383038
100430372306125472510001000100039816000301830373037241432895100010001000303730371110011000007300116112629100030383038303830383038
100430372306125472510001000100039816000301830373037241432895100010001000303730371110011000007300116112629100030383038303830383038
100430372406125472510001000100039816000301830373037241432895100010001000303730371110011000007300116112629100030383038303830383038

Test 2: Latency 1->2

Code:

  fcvtns v0.8h, v0.8h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020430037232010329547251010010010000100100005004277160030018300373003728264328745101002001000020010000300373003711102011009910010010000100007102161129633100001003003830038300383003830038
102053003723306129547251010010010000100100005004277160030018300373003728264328745101002001000020010000300373003711102011009910010010000100107101161129633100001003003830038300383003830038
102043003723306129547251010010010000100100005004277160030018300373003728264328745101002001000020010000300373003711102011009910010010000100007101161129633100001003003830038300383003830038
102043003723306129547251010010010000100100005004277160030018300373003728264328745101002001000020010000300373003711102011009910010010000100107101161129633100001003003830038300383003830038
1020430037241010329547251010010010000100100005004277160030018300373003728264328745101002001000020010000300373003711102011009910010010000100007101161129633100001003003830038300383003830038
102043003723306129547251010010010000100100005004277160030018300373003728264328745101002001000020010000300373003711102011009910010010000100007101161129633100001003003830038300383003830038
102043003723206129547251010010010000100101505004277160130018300373003728264328745101002001000020010000300373003711102011009910010010000100007101161129633100001003003830038300383003830038
102043003723306129547251010010010000100100005004277160130018300373003728264328745101002001000020010000300373003711102011009910010010000100007101161129633100001003003830038300383003830038
102043003723306129547251010010010000100100005004277160030018300373003728264328745101002001000020010000300373003711102011009910010010000100007101161129633100001003003830038300383003830038
102043003723306129547251010010010000100100005004277160030018300373003728264328745101002001000020010000300373003711102011009910010010000100007101161129633100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
100243003722500612954725100461010000101000050427716013001830037300372828672878610010201000020100003003730037111002110910101000010006403162229629010000103003830038300383003830038
100243003722500612954725100101010000101000050427716013001830037300372828632876710010201000020100003003730037111002110910101000010006402162229629010000103003830038300383003830038
100243003722500612954725100101010000101000050427716013001830037300372828632876710010201000020100003003730037111002110910101000010006402162229629010000103003830038300383003830038
100243003722500612954725100101010000101000050427716003001830037300372828632876710010201000020100003003730037111002110910101000010006402162229629010000103003830038300383003830038
100243003722500612954725100101010000101000050427716013001830037300372828632876710010201000020100003003730037111002110910101000010006402162229629010000103003830038300383003830038
100243003722400612954725100101010000101000050427716003001830037300372828632876710010201000020100003003730037111002110910101000010006402162229629010000103003830038300383003830038
1002430037225007262954725100101010000101000050428121603001830037300372828632876710010201000020100003003730037111002110910101000010006402162229629010000103003830038300383003830038
100243003722500612954725100101010000101000050427716013001830037300372828632876710010201000020100003003730037111002110910101000010006402162229629010000103003830038300383003830038
100243003722500612954725100101010000101015050427716013001830037300372828632876710613201000020100003003730037111002110910101000010306402162229629010000103003830038300383003830038
100243003722500612954725100101010000101000050427716013001830037300372828632876710010201000020100003003730037111002110910101000010006402162229629010000103003830038300383003830038

Test 3: throughput

Count: 8

Code:

  fcvtns v0.8h, v8.8h
  fcvtns v1.8h, v8.8h
  fcvtns v2.8h, v8.8h
  fcvtns v3.8h, v8.8h
  fcvtns v4.8h, v8.8h
  fcvtns v5.8h, v8.8h
  fcvtns v6.8h, v8.8h
  fcvtns v7.8h, v8.8h
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss instruction (0a)l2 tlb miss data (0b)18191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
802042003915500000003025801081008000810080020500640132020020200392003999776999080120200800322008003220039200391180201100991001008000010000000000111511821600200360800001002004020040200402004020040
802042003915500000003025801081008000810080020500640132120020200392003999776999080120200800322008003220039200391180201100991001008000010000000000111511801600200360800001002004020040200402004020040
802042003915500000003025801081008000810080020500640132020020200392003999776999080120200800322008003220039200391180201100991001008000010000001000111511801600200360800001002004020040200402004020040
802042003915600000003025801081008000810080020500640132020020200902003999776999080120200800322008003220039200391180201100991001008000010000000000111511801600200360800001002004020040200402004020040
8020420039155000000030258010810080008100800205006401320200202003920039997769990801202008003220080032200392003911802011009910010080000100000011000111511801600200360800001002004020040200402004020040
8020420039155000000023141738089210080794100803315226459380203502045020451100413710174808402008085120080769204542040781802011009910010080000100000000354501115274510336203690800001002045620395203962045320092
80204204551590108210567043025801081008000810080020500640132120020200392003999772310093809662048075820280770203982035191802011009910010080000100022100281502225251412389203320800001002052020464205132045220462
802042046315810188118879235491958078610680151105809315276472580203652004820048997169994801002008000020080000200482004811802011009910010080000100202002423501115274312437203801800001002046720517201532046320469
802042046515901099118870443172078099010080787102805265226465320201902060220527100444010235810352008091820480000200482004811802011009910010080000100000000400321115275713236203660800001002047120411205172046220524
802042050815900191067579236506280903101806991088034451164019602002920048200499976109986801282008003820080038200482004811802011009910010080000100000030390111511801600200360800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03l1i tlb fill (04)l2 tlb miss data (0b)1e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)accfd0l1i tlb miss demand (d4)d5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200391551004025800101080000108000050640000020020020039200399996310019800102080000208000020039200391180021109101080000100005021191331631282003680000102004020040200402004020040
80024200391551004025800101080000108000050640000120020020039200399996310019800102080000208000020039200391180021109101080000100035021241311631182003680000102004020040200402004020040
80024200391561006825800101080000108000050640000020020020039200399996310019800102080000208000020039200391180021109101080000100035021241311616322003680000102004020040200402004020040
80024200391561004025800101080000108000050640000020020020039200399996310019800102080000208000020039200391180021109101080000102035038241171622332003680000102004020040200402004020040
80024200391551027640258001010800001080000506400001200200200392003910005310019800102080000208000020039200391180021109101080000100005021211311634332003680000102004020040200402004020040
80024200391551004025800101080000108000050640000120020020039200399996310019800102080000208000020039200391180021109101080000100035021271311631322003680000102004020040200402004020040
80024200391551004025800101080000108000050640000020020020039200399996310019800102080000208000020039200391180021109101080000100105021181321630322003680000102004020040200402004020040
80024200391551004062802051080000108000050640000020020020039200399996310019800102080000208000020039200391180021109101080000100005021211331634342003680000102004020040200402004020040
800242003915510128225800101080000108000050640000120020020039200399996310019800102080000208000020039200391180021109101080000100005021241331634342003680000102024720040200402004020040
8002420039155101212425800101080000108000050640000020020020039200399996310019800102080000208000020039200391180021109101080000100005021211191634192003680000102004020040200402004020040