Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FCVTNU (scalar, D to D)

Test 1: uops

Code:

  fcvtnu d0, d0
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100430372406125472510001000100039816013018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
100430372496125472510001000100039816003018303730372414328951000100010003037303711100110003373116112629100030383038303830383038
100430372306125472510001000100039816003018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
100430372406125472510001000115039816013018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
100430372306125472510001000100039816003018303730372414328951000100010003037303711100110000673116112629100030383038303830383038
100430372306125472510001000100039816003018303730372414328951000100010003037303711100110000973116112629100030383038303830383038
100430372406125472510001000100039816003018303730372414328951000100010003037303711100110000973116112629100030383038303830383038
100430372306125472510001000100039816003018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
100430372408225472510001000100039816003018303730372414328951000100010003037303711100110000373116112629100030383038303830383038
100430372406125472510001000100039816003018303730372414328951000100010003037303711100110000073116112629100030383038303830383038

Test 2: Latency 1->2

Code:

  fcvtnu d0, d0
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020430037233019129547251010010010000100100005004277160130018300373003728264328745101002001000020010000300373003711102011009910010010000100420007101161129633100001003003830038300383003830038
1020430037232014529547251010010010000100100005004277160030018300373003728264328745101002001000020010000300373003711102011009910010010000100000007101161129633100001003003830038300383003830038
102043003723327454429547251010010010000100100005004277160030018300373003728264328745101002001000020010000300373003711102011009910010010000100000007101161129633100001003003830038300383003830038
102043003723306129547251010010010000100100005004277160130018300373003728264328745101002001000020010000300373003711102011009910010010000100000007101161129633100001003003830038300383003830038
1020430037233032429547251010010010000100100005004277160130018300373003728264328745101002001000020010000300373003711102011009910010010000100000107101161129633100001003003830038300383003830038
10204300372330295829547251010010010000100100005004277160130018300373003728264328745101002001000020010000300373003711102011009910010010000100000007101161129633100001003003830038300383003830038
102043003723306129547251010010010000100100005004277160030018300373003728264328745101002001000020010000300373003711102011009910010010000100002307101161129633100001003003830038300383003830038
102043003723306129547251010010010000100100005004277160030018300373003728264328745101002001000020010000300373003711102011009910010010000100000007101161129633100001003003830038300383003830038
102043003723306129547251010010010000100100005004277160030018300373003728264328745101002001000020010000300373003711102011009910010010000100000007101161129633100001003003830038300383003830038
1020430037233012429547251010010010000100100005004277160130018300373003728264328745101002001000020010000300373003711102011009910010010000100000007101161129633100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch mispred nonspec (cb)cfd5map dispatch bubble (d6)daddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024300372330336129547251001010100001010000504277160130018300373003728286328767100102010000201000030037300371110021109101010000100006402160222962910000103003830038300383003830038
1002430037233006129547251001010100001010000504277160030018300373003728286328767100102010000201000030037300371110021109101010000100006402160222962910000103003830038300383003830038
1002430037233006129547251001010100001010000504277160030018300373003728286328767100102010000201000030037300371110021109101010000100006402160222962910000103003830038300383003830038
1002430037233006129547251001010100001010000504277160130018300373003728286328767100102010000201000030037300371110021109101010000100006402160222962910000103003830038300383003830038
1002430037233006129547251001010100001010000504277160030018300373003728286328767101602010000201000030037300371110021109101010000100006402160222970110000103003830038300383003830038
1002430037233006129547251001010100001010000504277160030018300373003728286328767100102010000201000030037300371110021109101010000100006402160222962910000103003830038300383003830038
10024300372320072629547251001010100001010000504277160030018300373003728286328767100102010000201000030037300371110021109101010000100006402160222962910000103003830038300383003830038
1002430037233006129547251001010100001010000504277160030018300373003728286328767100102010000201000030037300371110021109101010000100006402160222962910000103003830038300383003830038
100243003722500171429547251001010100001010000504277160030018300373003728286328767100102010000201000030037300371110021109101010000100006402160222962910000103003830038300383003830038
1002430037225006129547251001010100001010000504277160030018300373003728286328767100102010000201000030037300371110021109101010000100006402160222962910000103003830038300383003830038

Test 3: throughput

Count: 8

Code:

  fcvtnu d0, d8
  fcvtnu d1, d8
  fcvtnu d2, d8
  fcvtnu d3, d8
  fcvtnu d4, d8
  fcvtnu d5, d8
  fcvtnu d6, d8
  fcvtnu d7, d8
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk instruction (07)1e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)a9acbranch cond mispred nonspec (c5)branch ret indir mispred nonspec (c8)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420039155145030258010810080008100800205006401321201892003920039997706999080120200800322008003220039200391180201100991001008000010000001011511801600200360800001002004020040200402004020040
802042003915600030268011610080016100800285006401961200292004820048997609998680128200800382008003820048200481180201100991001008000010000002022512912311200450800001002004920049200492004920049
802042025615500064278011610080016100800285006401961200292004820049997609998680128200800382008003820048200481180201100991001008000010000002022512812311200450800001002004920049200502005020049
802042004815500064268011610080016100800285006401961200292004820049997609998680128200800382008003820048200481180201100991001008000010000002022512912311200460800001002004920049200502004920050
8020420049155000642780116100800161008002850064019612002920048200489976010998680128200800382008003820048200481180201100991001008000010000002022512812311200460800001002004920049200492004920050
802042004815600030258010810080008100800205006401321200202003920039997706999080120200800322008003220039200391180201100991001008000010000001011511801600200360800001002004020040200402004020040
802042003916103094258010810080008100800205006401321200202003920039997706999080120200800322008003220039200391180201100991001008000010000001011511811600200360800001002004020040200402004020040
802042003915600030258010810080008100800205006401321200722003920039997706999080120200800322008045220039200391180201100991001008000010000001011511801600200360800001002004020040200402004020040
802042003915500030258010810080008100800205006401321200202003920039997706999080120200800322008003220039200391180201100991001008000010003001011511801600200361800001002004020040200402004020040
8020420039155000302580108100800081008002050064013212002020039200399977014999080120200800322008003220039200391180201100991001008000010000001011511801600200360800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
800242003915504025800101080000108000050640000002002002003920039999631001980010208000020800002003920039118002110910108000010005020516442003680000102004020040200402004020040
800242003915504025800101080000108000050640000002002002003920039999631001980010208000020800002003920039118002110910108000010005020316342003680000102004020040200402004020040
800242003915504025800101080000108000050640000002002002003920039999631001980010208000020800002003920039118002110910108000010005020616872003680000102004020040200402004020040
800242003915594025800101080000108000050640000002002002003920039999631001980010208000020800002003920039118002110910108000010005020616772003680000102004020040200402004020040
800242003915604025800101080000108000050640000002002002003920039999631001980010208000020800002003920039118002110910108000010005020316772003680000102004020040200402004020040
800242003915504025800101080000108000050640000002002002003920039999631001980010208000020800002003920039118002110910108000010035020416742003680000102004020040200402004020040
800242003915504025800101080000108000050640000002002002003920039999631001980010208000020800002003920039118002110910108000010005020716342003680000102004020040200402004020040
8002420039155070525800101080000108000050640000002002002003920039999631001980010208000020800002003920039118002110910108000010005020416762003680000102004020040200402004020040
800242003915504025800101080000108000050640000002002002003920039999631001980010208000020800002003920039118002110910108000010005020616342003680000102004020040200402004020040
8002420039155042825800101080000108000050640000002002002003920039999631001980010208000020800002003920039118002110910108000010005020416742003680000102004020040200402004020040