Apple M1 Microarchitecture Research by Dougall Johnson

Firestorm: Overview | Base Instructions | SIMD and FP Instructions
Icestorm:  Overview | Base Instructions | SIMD and FP Instructions

FCVTNU (scalar, D to W)

Test 1: uops

Code:

  fcvtnu w0, d0
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 3.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 2.000

retire (01)cycle (02)030b1e3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch fp/simd (57)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op fp/simd (7e)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst integer (97)a8accfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
20045414004325300010002000200018000152254154124832742000200020005415411110011000007321611538100010001000542542542542542
20045414004325300010002000200018000152254154124832742000200020005415411110011000007311611538100010001000542542542542542
20045414008525300010002000200018000152254154124832742000200020005415411110011000007311611538100010001000542542542542542
20045414004325300010002000200018000152254154124832742000200020005415411110011000007311611538100010001000542542542542542
20045414004325300010002000200018000152254154124832742000200020005415411110011000007311611538100010001000542542542542542
20045414034325300010002000200018000152254154124832742000200020005415411110011000007311611538100010001000542542542542542
20045414004325300010002000200018000152254154124832742000200020005415411110011000007311612538100010001000542542542542542
20045414004325300010002000200018000152254154124832742000200020005415411110011000007311611538100010001000542542542542542
20045414004325300010002000200018000152254154124832742000200020005415411110011000007311611538100010001000542542542542542
20045414004325300010002000200018000152254154124832742000200020005415411110011000007311612538100010001000542542542542542

Test 2: Latency 1->2 roundtrip

Code:

  fcvtnu w0, d0
  fmov d0, x0
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 13.0038

retire (01)cycle (02)030b18191e1f3f4f51inst issue (52)~issue int (53)~issue fp/simd (54)~issue ld/st (55)~dispatch int (56)~dispatch fp/simd (57)~dispatch ld/st (58)huge thing int (59)huge thing ld/st (5a)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op ld/st (7d)~map op fp/simd (7e)~map lookup int (7f)~map lookup ld/st (80)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa0a1a6a8acc2c5branch mispredict (cb)cdcfd0d5d6ddinst fetch restart (de)e0? int output thing (e9)ld/st retires (ed)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
30204130038974000001300231194172540100101002000010000100200001000050062149791480103411300131300381300381254837126242301002001000220006200100022000613003813003811202011009910010100100001000010000000111131801161112953310000100001000010100130039130039130039130039130042
30204130038974000001300231194172540100101002000010000100200001000050062150271480103411300131300381300381254837126241301002001000220006200100662025513003813003811202011009910010100100001000010000000111131802162212952510000100001000010100130039130039130039130039130039
30204130038974000001300261194172540100101002000010000100200001000050062149791480103411300131300381300411254763126246301002001000020000200100002000013003813003811202011009910010100100001000010000000000131012162212952510000100001000010100130039130039130039130039130039
30204130038974000001300231194172540100101002000010000100200001000050062154451480103411300131300381300381254763126246301002001000020000200100002000013003813004111202011009910010100100001000010000000000131012162212952510000100001000010100130039130039130039130039130039
30204130038974000001300231194172540100101002000010000100200001000050062149791480103411300131300381300381254763126246301002001000020000200100002000013003813003811202011009910010100100001000010000000000131012162212952510000100001000010100130039130039130039130039130039
30204130038974000001300231194172540100101002000010000100200001000050062149791480103411300131300381300381254763126246301002001000020000200100002000013003813003811202011009910010100100001000010000000000131012162212952510000100001000010100130039130039130039130039130039
30204130038974000001300231194172540100101002000010000100200001000050062149791480103411300131300381300381254763126246301002001000020000200100622000013003813003811202011009910010100100001000010000000000131012162212952510000100001000010100130039130039130039130039130039
30204130038974000901300231194172540100101002000010000100200001000050062149791480103411300131300381300381254763126246301002001000020000200100002000013003813003811202011009910010100100001000010000000000131012162212952510006100001000010100130039130039130039130039130039
30204130038974000001300231194172540100101002000010000100200001000050062149791480103411300131300381300381254763126246301002001000020000200100002000013003813003811202011009910010100100001000010000000000131012162212952510000100001000010100130039130039130039130039130039
30204130038974000001300231194172540100101002000010000100200001000050062149791480103411300131300381300381254763126246301002001000020000200100002000013003813003811202011009910010100100001000010000000000131012162212952510000100001000010100130039130039130041130039130039

1000 unrolls and 10 iterations

Result (median cycles for code): 13.0038

retire (01)cycle (02)03181e3a3f4f51inst issue (52)~issue int (53)~issue fp/simd (54)~issue ld/st (55)~dispatch int (56)~dispatch fp/simd (57)~dispatch ld/st (58)huge thing int (59)huge thing ld/st (5a)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op ld/st (7d)~map op fp/simd (7e)~map lookup int (7f)~map lookup ld/st (80)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa6a8acc5branch mispredict (cb)cfd5d6ddinst fetch restart (de)e0? int output thing (e9)ebld/st retires (ed)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
300241300389740001300231194172540010100102000010000102000010000506214979148000251130013130038130038125498312626830010201000020000201000020000130038130038112002110910100101000010100000000127011621129525100000100001000010010130039130039130039130039130039
3002413003897409013002311941725400101001020000100001020000100005062149791480002511300131300381300381255413126268300102010000200002010000200001300381300381120021109101001010000101000902999500127001613129525100000100001000010010130039130039130039130039130039
3002413004097420013013911968017340046100112000010000102000010000506214979148000251130013130038130038125498312626830010201000020000201000020000130038130038112002110910100101000010100000000127011611129525100000100001000010010130045130039130039130039130039
300241300389740001300231194172540010100102000010000102000010000506214979148000251130013130038130038125498312626830010201000020000201000020000130038130038112002110910100101000010100000000127011611129525100000100001000010010130039130039130039130039130039
300241300389730001300231194172540010100102000010000102000010000506214979148000251130013130038130038125498312626830010201000020000201000020000130038130038112002110910100101000010100000000127011611129525100000100001000010010130039130039130039130039130039
300241300389740001300231194172540010100102000010000102000010000506214979148000251130013130038130039125498312626830010201000020000201000020000130038130038112002110910100101000010100000000127011612129525100000100001000010010130039130039130039130039130039
30024130038974000130023119417254001010010200001000010200001000050621497914800025113001313003813003812549831262683001020100002000020100002000013003813004311200211091010010100001010000018910127011611129525100000100001000010010130039130039130039130039130039
300241300389740001300231194172540010100102000010000102000010000506214979148000251130013130038130038125498312626830010201000020000201000020000130038130135112002110910100101000010100000000127011611129525100000100001000010010130039130039130039130039130039
300241300389740001300231194173640010100102000010000102000010000506214979148000251130013130038130038125498312630930010201000020000201000020000130038130038112002210910100101000010100000600127011611129525100000100001000010010130039130039130039130039130039
300241300389740001300231194172540010100102000010000102000010000506214979148000251130013130038130038125498312626830010201000020000201000020000130038130038112002110910100101000010100000000127011621129525100000100001000010010130039130039130039130039130057

Test 3: throughput

Count: 8

Code:

  fcvtnu w0, d8
  fcvtnu w1, d8
  fcvtnu w2, d8
  fcvtnu w3, d8
  fcvtnu w4, d8
  fcvtnu w5, d8
  fcvtnu w6, d8
  fcvtnu w7, d8
  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

retire (01)cycle (02)030918191e1f3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)9fa0a1a6a8a9acc5branch mispredict (cb)cdcfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
16020440062310000003225240104801001600041001600205001440132140022400414004119977619992160120200160032200160032400414004111802011009910080100100000500111511701600400388000080000801004004240042400424004240042
16020440041310000003225240104801001600041001600205001440132140022400414004119977619992160120200160032200160032400414004111802011009910080100100000000111511701600400388000080000801004004240042400424004240042
160204400413100000068025240104801001600041001600205001440132140022400414004119977619992160120200160032200160032400414004111802011009910080100100000000111511701600400388000080000801004004240042400424004240042
16020440041310000003225240104801001600041001600205001440132140022400414004119977619992160120200160032200160032400414004111802011009910080100100000000111511701600400388000080000801004004240042400424004240042
16020440041311000003225240104801001600041001600205001440132140022400414004119977619992160120200160032200160032400414004111802011009910080100100000000111511701600400388000080000801004004240042400424004240042
16020440041311000003225240104801001600041001600205001440132140022400414004119977619992160120200160032200160032400414004111802011009910080100100000000111511701600400388000080000801004004240042400424004240042
16020440041311000003225240104801001600041001600205001440132040022400414004119977619992160120200160032200160032400414004111802011009910080100100000000111511701600400388000080000801004004240042400424004240042
16020440041310000003225240104801001600041001600205001440132140022400414004119977619992160120200160032200160032400414004111802011009910080100100000000111511701600400388000080000801004004240042400424004240042
160204400413100000040925240104801001600041001600205001440132040022400414004119977619992160120200160032200160032400414004111802011009910080100100000000111511701600400388000080000801004004240042400424004240042
160204400413000006010125240104801001600041001600205001440132140022400414004119977619992160120200160032200160032400414004111802011009910080100100000000111511701611406288076480000801004068340678407504068940762

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

retire (01)cycle (02)0318191e1f3a3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)9fa8accficache miss (d3)d5d6daddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
16002440054300000031952524001080010160000101600005014400001400224004140041199963200211600102016000020160000400414004111800211091080010100050200216024400388000080000800104004240042400424004240042
16002440041300000002562524001080010160000101600005014400001400224004140041199963200211600102016000020160000400414004111800211091080010100050200216042400388000080000800104004240042400424004240042
16002440041300000011472524001080010160000101600005014400001400224004140041199963200211600102016000020160000400414004111800211091080010100050200216024400388000080000800104004240042400424004240042
16002440041300000011892524001080010160000101600005014400000400224004140041199963200211600102016000020160000400414004111800211091080010100050200416024400388000080000800104004240042400424004240042
16002440041299000018672524001080010160000101600005014400000400224004140041199963200211600102016000020160000400414004111800211091080010100050200416042400388000080000800104004240042400424004240042
16002440041300000012752524001080010160000101600005014400001400224004140041199963200211600102016000020160000400414004111800211091080010102050200216024400388000080000800104004240042400424004240042
16002440041300000013662524001080010160000101600005014400001400224004140041199963200211600102016000020160000400414004111800211091080010100050200416042400388029380000800104004240042400424004240042
16002440041300000011892524001080010160000101608165014400001400224004140041199963200211600102016000020160000400414004111800211091080010100050200416042400388000080000800104004240042400424004240042
16002440041300000019342524001080010160000101600005014400001400224004140041199963200211600102016000020160000400414004111800211091080010100050200416042400388000080000800104004240042400424004240042
16002440041311000011472524001080010160000101600005014400000400224004140041199963200211600102016000020160000400414004111800211091080010100050200616042400388000080000800104004240042400424004240042