Apple M1 Microarchitecture Research by Dougall Johnson

Firestorm: Overview | Base Instructions | SIMD and FP Instructions
Icestorm:  Overview | Base Instructions | SIMD and FP Instructions

FCVTNU (scalar, D to X)

Test 1: uops

Code:

  fcvtnu x0, d0
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 3.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 2.000

retire (01)cycle (02)0308091e1f3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch fp/simd (57)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op fp/simd (7e)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst integer (97)a0a8a9accfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
2004541400120432530001000200020001800005225415412483274200020002000541541111001100000007311611538100010001000542542542542542
200454150030432530001000200020001800005225415412483274200020002000541541111001100000007311611538100010001000542542542542542
200454150000432530001000200020001800005225415412483274200020002000541541111001100001007311611538100010001000542542542542542
200454140000432530001000200020001800005225415412483274200020002000541541111001100000007311611538100010001000542542542542542
200454140000432530001000200020001800005225415412483274200020002000541541111001100000007311611538100010001000542542542542542
200454150000432530001000200020001800005225415412483274200020002000541541111001100000007311611538100010001000542542542542542
200454140000432530001000200020001800005225415412483274200020002000541541111001100000007311611538100010001000542542542542542
200454140000432530001000200020001800005225415412483274200020002000541541111001100000007311611538100010001000542542542542542
200454140000432530001000200020001800005225415412483274200020002000541541111001100000007311611538100010001000542542542542542
2004541400001142530001000200020001800005225415412483274200020002000541541111001100000007311611538100010001000542542542542542

Test 2: Latency 1->2 roundtrip

Code:

  fcvtnu x0, d0
  fmov d0, x0
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 13.0038

retire (01)cycle (02)0308090b181e1f3f4f51inst issue (52)~issue int (53)~issue fp/simd (54)~issue ld/st (55)~dispatch int (56)~dispatch fp/simd (57)~dispatch ld/st (58)huge thing int (59)huge thing ld/st (5a)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op ld/st (7d)~map op fp/simd (7e)~map lookup int (7f)~map lookup ld/st (80)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa0a6a8a9acbranch mispredict (cb)cfd0d5d6ddinst fetch restart (de)e0? int output thing (e9)ld/st retires (ed)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
302041300389730000001300231194172540100101002000010000123200001000050062164671480103411300131300381300381254763126249301002001000020000200100002000013003813003811202011009910010100100001000100000000131012162212952510000100001000010100130039130039130039130039130039
302041300389740000001300231194172540100101002000010000100200001000050062149791480103411300131300381300381254763126246301002001000020000200100002000013003813003811202011009910010100100001000100000000131012162212952510000100001000010100130039130039130039130039130039
3020413003897400000013002311941725401001010020000100001002000010000500621497914801034113001313003813003812547631262463010020010000200002001000020000130038130038112020110099100101001000010001000012000131012162212952510000100001000010100130039130039130039130039130039
302041300389740000001300231194172540100101002000010000100200001000050062149791480103411300131300381300381254763126246301002021000020000200100002000013003813003811202011009910010100100001000100000000131012162212952510014100001000010100130039130039130039130039130039
302041300389740000001300231194172540100101002000010000100200001000050062149791480103411300131300381300381254763126254301002001000020000200100002000013003813003811202011009910010100100001000100000000131012162212952510000100001000010100130039130039130039130039130039
3020413003810080000001300231194142540100101002000010000100200001000050062149791480103411300131300381300381254763126246301002001000020000200100002000013003813003811202011009910010100100001000100000000131012162212952510000100001000010100130039130039130039130039130039
3020413003897400001201300231194172540100101002000010000100200001000050062149791480103411300131300381300381254763126246301002121012220000200100002000013003813003811202011009910010100100001000100000000131012162212952510000100001000010100130039130039130039130039130497
302041305409760110086213002311984515240151101162000310000100200001000050062149791480103411300131306391305541257029126246301002001000020000200100002000013064013063731202011009910010100100001000100000000131012162212952510000100001000010100130039130039130039130039130039
302041300389740000001300231194172540100101002000010000100200001000050062149791480103411300131300401300381254783126246301002001000020000200100002000013003813003811202011009910010100100001000100000000131012162212952510000100001000010100130039130039130039130048130039
302041300389740000001300231194172540100101002000010000100200001000050062149791480103411300131300381300381254793126246301002001000020000200100002000013003813004111202011009910010100100001000100000000131012162212958010000100001000010100130039130039130039130039130039

1000 unrolls and 10 iterations

Result (median cycles for code): 13.0038

retire (01)cycle (02)03080b18191e1f3f4f51inst issue (52)~issue int (53)~issue fp/simd (54)~issue ld/st (55)~dispatch int (56)~dispatch fp/simd (57)~dispatch ld/st (58)huge thing int (59)huge thing ld/st (5a)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op ld/st (7d)~map op fp/simd (7e)~map lookup int (7f)~map lookup ld/st (80)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa0a6a8a9acc2branch mispredict (cb)cdcfd0d5d6daddinst fetch restart (de)e0? int output thing (e9)ld/st retires (ed)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
30024130038100800000013002311941825400101001020000100001020000100005062149791480002501300131300381300381254983126268300102010000200002010000200001300381300381120021109101001010000100100000000001270564801112952510000100001000010010130039130039130039130039130039
30024130038100800000013002311941725400101001020000100001020000100005062149791480002501300131300381300381254983126268300102010000200002010000200001300381300381120021109101001010000100100000000001271011601112952510000100001000010010130039130039130039130039130039
30024130038100800000013002311941725400101001020000100001020000100005062149791480002511300131300381300381254983126268300102010000200002010000200001300381300381120021109101001010000100100000000001270011601112952510000100001000010010130039130039130039130039130039
30024130038100800000013002311941725400101001020000100001020000100505062149791480002501300131300381300381254983126268300102010000200002010000200001300381300381120021109101001010000100100000000001270011601112952510000100001000010010130039130039130039130039130039
3002413003897400000013002311941725400101001020000100001020000100005062149791480002501300181300741300801254983126268300102010000200002010000200001300401300381120021109101001010000100100000000001270011601112952510000100001000010010130039130039130039130039130039
3002413003897400009013002311941725400101001020000100001020000100005062149791480002511300131300381300381254983126268300102010000200002010000200001300381300381120021109101001010000100100001000001270011601112952510000100001000010010130039130039130039130039130039
3002413003897400000013030011941725400101001020000100001020000100005062149791480002501300131300381300381254983126268300102010000200002010000200001300381300381120021109101001010000100100000000001270011601112952510000100001000010010130039130039130039130039130039
300241300389740000001300231194172540010100102000010000102000010000506214979148000250130013130038130038125498312626930010201000020000201000020000130038130038112002210910100101000010010000001980001270011601112952510000100001000010010130082130043130039130039130039
3002413003897400000013002311941725400101001020000100001020000100005062149791480002501300131300381300381254983126335300102010000200002010000200001300381300381120021109101001010000100100000000001270021601112952510000100001000010010130039130039130068130039130039
3002413003897400000013002311941725400101001020000100001020000100005062149791480002511300131300381300381254983126320300102010000200002010000200001300381300381120021109101001010000100100000000001270011601112952510000100001000010010130039130039130039130039130039

Test 3: throughput

Count: 8

Code:

  fcvtnu x0, d8
  fcvtnu x1, d8
  fcvtnu x2, d8
  fcvtnu x3, d8
  fcvtnu x4, d8
  fcvtnu x5, d8
  fcvtnu x6, d8
  fcvtnu x7, d8
  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

retire (01)cycle (02)03080b0f18191e1f3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696d6edispatch stall (70)74scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)9fa1a6a8a9acc2c5cabranch mispredict (cb)cdcfd5d6ddinst fetch restart (de)e0? int output thing (e9)ea? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
160204400663100000000322524010480100160004100160020500144013204002240041400411997706199921601202001600322001600324004140041118020110099100801001000069015010115117116004003880000080000801004004240042400424004240042
160204400413100000000602252401048010016000410016002050014401320400224004140041199770619992160120200160032200160032400414004111802011009910080100100005106010115117016004003880092080000801004004240042400424004240042
16020440041310000000032252401048010016000410016002050014401320400224012740041199770619992160120200160032200160032400414004111802011009910080100100002100010115117016004003880000080000801004004240042400424004240042
1602044004131000000150322322423688066216076410016184253414528140408544112640599202840732043816275420016250020616280241161407681618020110099100801001002015054950101152430151004049681460080000801004125541312408484124740042
16020440041310000004260491927824127281234162360105160844500146235414105641139411592033701192065716322620016306220016287440767412221618020110099100801001000000705410115117016004003880000080000801004012440356410004114941140
160204411423161006012009684647440245063815401629481041632585411468791140734413784121520384013420740163394208162072210163476413964069217180201100991008010010024009350010115117016004119981146080000801004116041315411414131241160
16020441382319010171822561584258926240116801041600121001600285001440202040096400514013320209092057316012820016003820016043840213402122180201100991008010010000106020225127124214004880004080000801004005240053400524005240052
16020440051375000000066262401168010416001210016002850014402020400324005140051199760919989160128200160038200160038400524005111802011009910080100100003800020225127124114004880004080000801004005340052400524005240052
160204400523100000000467262401168010416001210016002850014402020400324005240052199760919989160128200160038200160038400514005111802011009910080100100001206020225128124114004880004080000801004005240052400524005240053
1602044005131100000006627240116801041600121001600285001440202040032400514005119976091998916012820016003820016003840052400511180201100991008010010000703020225127124114004880004080000801004005240052400524005240053

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

retire (01)cycle (02)03070a1e3a3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)9fa6a8accfd5d6ddinst fetch restart (de)e0? int output thing (e9)ea? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
1600244004230011014825240010800921600001016000050144000014002240041400411999632002116001020160000201600004004140041118002110910800101000815021201616194003880000080000800104004240042400424004240042
1600244004131011014825240010800101600001016000050144000004002240041400411999632002116001020160000201600004004140041118002110910800101000210502115161584003880000080000800104004240042400424004240042
16002440041300110148252400108001016000010160000501440000140022400414004119996320021160010201600002016000040041400411180021109108001010002345021151616194003880000080000800104004240042400424004240042
16002440041300110148252400108001016000010160000501440000140022400414004119996320021160010201600002016000040041400411180021109108001010002075021161616144003880000080000800104004240042400424004240042
160024400413001101482524001080010160000101600005014400000400224004140041199963200211600102016000020160000400414004111800211091080010100005021171613164003880000080000800104004240042400424004240042
1600244004130011014825240010800101600001016000050144000014002240041400411999632002116001020160000201600004004140041118002110910800101001215124151614164003880000080000800104004240042400424004240042
1600244004129911619025240010800101600001016000050144000004002240041400411999632002116001020160000201600004004140041118002110910800101020545021101615164010380962080000800104004240529402754043840989
160024412403093257148252400108001016000010160000501440000040022400414004119996320021160010201600002016000040041400411180021109108001010002135021161614174003880000080000800104004240042400424004240042
1600244004130011014825240010800101600001016000050144000014002240041400411999632002116001020160000201600004004140041118002110910800101000995021161617174003880000080000800104004240042400424004240042
16002440041300110148252400108001016000010160000501440000140022400414004119996320021160010201600002016000040041400411180021109108001010001355021151615164003880000080000800104004240042400424004240042