Firestorm: FCVTNU (scalar, D to X) measurements

Code:

  fcvtnu x0, d0

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 3.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 2.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	l1d tlb access (a0)	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
2004	541	4	0	0	12	0	43	25	3000	1000	2000	2000	18000	0	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	0	0	73	1	16	1	1	538	1000	1000	1000	542	542	542	542	542
2004	541	5	0	0	3	0	43	25	3000	1000	2000	2000	18000	0	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	0	0	73	1	16	1	1	538	1000	1000	1000	542	542	542	542	542
2004	541	5	0	0	0	0	43	25	3000	1000	2000	2000	18000	0	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	1	0	0	73	1	16	1	1	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	0	0	0	43	25	3000	1000	2000	2000	18000	0	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	0	0	73	1	16	1	1	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	0	0	0	43	25	3000	1000	2000	2000	18000	0	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	0	0	73	1	16	1	1	538	1000	1000	1000	542	542	542	542	542
2004	541	5	0	0	0	0	43	25	3000	1000	2000	2000	18000	0	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	0	0	73	1	16	1	1	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	0	0	0	43	25	3000	1000	2000	2000	18000	0	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	0	0	73	1	16	1	1	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	0	0	0	43	25	3000	1000	2000	2000	18000	0	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	0	0	73	1	16	1	1	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	0	0	0	43	25	3000	1000	2000	2000	18000	0	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	0	0	73	1	16	1	1	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	0	0	0	114	25	3000	1000	2000	2000	18000	0	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	0	0	73	1	16	1	1	538	1000	1000	1000	542	542	542	542	542

Test 2: Latency 1->2 roundtrip

Code:

  fcvtnu x0, d0
  fmov d0, x0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 13.0038

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	1e	1f	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	branch mispred nonspec (cb)	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30204	130038	973	0	0	0	0	0	0	130023	119417	25	40100	10100	20000	10000	123	20000	10000	500	6216467	14801034	1	130013	130038	130038	125476	3	126249	30100	200	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	1310	1	2	16	2	2	129525	10000	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	974	0	0	0	0	0	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	1	130013	130038	130038	125476	3	126246	30100	200	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	1310	1	2	16	2	2	129525	10000	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	974	0	0	0	0	0	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	1	130013	130038	130038	125476	3	126246	30100	200	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	10000	12	0	0	0	1310	1	2	16	2	2	129525	10000	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	974	0	0	0	0	0	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	1	130013	130038	130038	125476	3	126246	30100	202	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	1310	1	2	16	2	2	129525	10014	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	974	0	0	0	0	0	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	1	130013	130038	130038	125476	3	126254	30100	200	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	1310	1	2	16	2	2	129525	10000	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	1008	0	0	0	0	0	0	130023	119414	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	1	130013	130038	130038	125476	3	126246	30100	200	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	1310	1	2	16	2	2	129525	10000	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	974	0	0	0	0	12	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	1	130013	130038	130038	125476	3	126246	30100	212	10122	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	1310	1	2	16	2	2	129525	10000	10000	10000	10100	130039	130039	130039	130039	130497
30204	130540	976	0	1	1	0	0	862	130023	119845	152	40151	10116	20003	10000	100	20000	10000	500	6214979	14801034	1	130013	130639	130554	125702	9	126246	30100	200	10000	20000	200	10000	20000	130640	130637	3	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	1310	1	2	16	2	2	129525	10000	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	974	0	0	0	0	0	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	1	130013	130040	130038	125478	3	126246	30100	200	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	1310	1	2	16	2	2	129525	10000	10000	10000	10100	130039	130039	130039	130048	130039
30204	130038	974	0	0	0	0	0	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	1	130013	130038	130038	125479	3	126246	30100	200	10000	20000	200	10000	20000	130038	130041	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	1310	1	2	16	2	2	129580	10000	10000	10000	10100	130039	130039	130039	130039	130039

1000 unrolls and 10 iterations

Result (median cycles for code): 13.0038

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch mispred nonspec (cb)	cd	cf	d0	d5	map dispatch bubble (d6)	da	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30024	130038	1008	0	0	0	0	0	0	130023	119418	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	0	130013	130038	130038	125498	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	0	0	0	1270	5	6	48	0	1	1	129525	10000	10000	10000	10010	130039	130039	130039	130039	130039
30024	130038	1008	0	0	0	0	0	0	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	0	130013	130038	130038	125498	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	0	0	0	1271	0	1	16	0	1	1	129525	10000	10000	10000	10010	130039	130039	130039	130039	130039
30024	130038	1008	0	0	0	0	0	0	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	1	130013	130038	130038	125498	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	0	0	0	1270	0	1	16	0	1	1	129525	10000	10000	10000	10010	130039	130039	130039	130039	130039
30024	130038	1008	0	0	0	0	0	0	130023	119417	25	40010	10010	20000	10000	10	20000	10050	50	6214979	14800025	0	130013	130038	130038	125498	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	0	0	0	1270	0	1	16	0	1	1	129525	10000	10000	10000	10010	130039	130039	130039	130039	130039
30024	130038	974	0	0	0	0	0	0	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	0	130018	130074	130080	125498	3	126268	30010	20	10000	20000	20	10000	20000	130040	130038	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	0	0	0	1270	0	1	16	0	1	1	129525	10000	10000	10000	10010	130039	130039	130039	130039	130039
30024	130038	974	0	0	0	0	9	0	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	1	130013	130038	130038	125498	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	0	10000	1	0	0	0	0	0	1270	0	1	16	0	1	1	129525	10000	10000	10000	10010	130039	130039	130039	130039	130039
30024	130038	974	0	0	0	0	0	0	130300	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	0	130013	130038	130038	125498	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	0	0	0	1270	0	1	16	0	1	1	129525	10000	10000	10000	10010	130039	130039	130039	130039	130039
30024	130038	974	0	0	0	0	0	0	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	0	130013	130038	130038	125498	3	126269	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20022	10	9	10	10010	10000	10	0	10000	0	0	198	0	0	0	1270	0	1	16	0	1	1	129525	10000	10000	10000	10010	130082	130043	130039	130039	130039
30024	130038	974	0	0	0	0	0	0	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	0	130013	130038	130038	125498	3	126335	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	0	0	0	1270	0	2	16	0	1	1	129525	10000	10000	10000	10010	130039	130039	130068	130039	130039
30024	130038	974	0	0	0	0	0	0	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	1	130013	130038	130038	125498	3	126320	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	0	0	0	1270	0	1	16	0	1	1	129525	10000	10000	10000	10010	130039	130039	130039	130039	130039

Test 3: throughput

Count: 8

Code:

  fcvtnu x0, d8
  fcvtnu x1, d8
  fcvtnu x2, d8
  fcvtnu x3, d8
  fcvtnu x4, d8
  fcvtnu x5, d8
  fcvtnu x6, d8
  fcvtnu x7, d8

Initialization

  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	0f	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	rob full (74)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch call indir mispred nonspec (ca)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	40066	310	0	0	0	0	0	0	0	32	25	240104	80100	160004	100	160020	500	1440132	0	40022	40041	40041	19977	0	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	69	0	15	0	1	0	1	1	5117	1	16	0	0	40038	80000	0	80000	80100	40042	40042	40042	40042	40042
160204	40041	310	0	0	0	0	0	0	0	602	25	240104	80100	160004	100	160020	500	1440132	0	40022	40041	40041	19977	0	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	51	0	6	0	1	0	1	1	5117	0	16	0	0	40038	80092	0	80000	80100	40042	40042	40042	40042	40042
160204	40041	310	0	0	0	0	0	0	0	32	25	240104	80100	160004	100	160020	500	1440132	0	40022	40127	40041	19977	0	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	21	0	0	0	1	0	1	1	5117	0	16	0	0	40038	80000	0	80000	80100	40042	40042	40042	40042	40042
160204	40041	310	0	0	0	0	0	15	0	32	232	242368	80662	160764	100	161842	534	1452814	0	40854	41126	40599	20284	0	73	20438	162754	200	162500	206	162802	41161	40768	16	1	80201	100	99	100	80100	100	2	0	15	0	5495	0	1	0	1	1	5243	0	151	0	0	40496	81460	0	80000	80100	41255	41312	40848	41247	40042
160204	40041	310	0	0	0	0	0	426	0	4919	278	241272	81234	162360	105	160844	500	1462354	1	41056	41139	41159	20337	0	119	20657	163226	200	163062	200	162874	40767	41222	16	1	80201	100	99	100	80100	100	0	0	0	0	705	4	1	0	1	1	5117	0	16	0	0	40038	80000	0	80000	80100	40124	40356	41000	41149	41140
160204	41142	316	1	0	0	6	0	1200	968	4647	440	245063	81540	162948	104	163258	541	1468791	1	40734	41378	41215	20384	0	134	20740	163394	208	162072	210	163476	41396	40692	17	1	80201	100	99	100	80100	100	2	4	0	0	9350	0	1	0	1	1	5117	0	16	0	0	41199	81146	0	80000	80100	41160	41315	41141	41312	41160
160204	41382	319	0	1	0	17	18	2256	1584	2589	26	240116	80104	160012	100	160028	500	1440202	0	40096	40051	40133	20209	0	9	20573	160128	200	160038	200	160438	40213	40212	2	1	80201	100	99	100	80100	100	0	0	1	0	6	0	2	0	2	2	5127	1	24	2	1	40048	80004	0	80000	80100	40052	40053	40052	40052	40052
160204	40051	375	0	0	0	0	0	0	0	66	26	240116	80104	160012	100	160028	500	1440202	0	40032	40051	40051	19976	0	9	19989	160128	200	160038	200	160038	40052	40051	1	1	80201	100	99	100	80100	100	0	0	38	0	0	0	2	0	2	2	5127	1	24	1	1	40048	80004	0	80000	80100	40053	40052	40052	40052	40052
160204	40052	310	0	0	0	0	0	0	0	467	26	240116	80104	160012	100	160028	500	1440202	0	40032	40052	40052	19976	0	9	19989	160128	200	160038	200	160038	40051	40051	1	1	80201	100	99	100	80100	100	0	0	12	0	6	0	2	0	2	2	5128	1	24	1	1	40048	80004	0	80000	80100	40052	40052	40052	40052	40053
160204	40051	311	0	0	0	0	0	0	0	66	27	240116	80104	160012	100	160028	500	1440202	0	40032	40051	40051	19976	0	9	19989	160128	200	160038	200	160038	40052	40051	1	1	80201	100	99	100	80100	100	0	0	7	0	3	0	2	0	2	2	5127	1	24	1	1	40048	80004	0	80000	80100	40052	40052	40052	40052	40053

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	1e	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	40042	300	1	1	0	1	48	25	240010	80092	160000	10	160000	50	1440000	1	40022	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	81	5021	20	16	16	19	40038	80000	0	80000	80010	40042	40042	40042	40042	40042
160024	40041	310	1	1	0	1	48	25	240010	80010	160000	10	160000	50	1440000	0	40022	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	210	5021	15	16	15	8	40038	80000	0	80000	80010	40042	40042	40042	40042	40042
160024	40041	300	1	1	0	1	48	25	240010	80010	160000	10	160000	50	1440000	1	40022	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	234	5021	15	16	16	19	40038	80000	0	80000	80010	40042	40042	40042	40042	40042
160024	40041	300	1	1	0	1	48	25	240010	80010	160000	10	160000	50	1440000	1	40022	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	207	5021	16	16	16	14	40038	80000	0	80000	80010	40042	40042	40042	40042	40042
160024	40041	300	1	1	0	1	48	25	240010	80010	160000	10	160000	50	1440000	0	40022	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	0	5021	17	16	13	16	40038	80000	0	80000	80010	40042	40042	40042	40042	40042
160024	40041	300	1	1	0	1	48	25	240010	80010	160000	10	160000	50	1440000	1	40022	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	1	21	5124	15	16	14	16	40038	80000	0	80000	80010	40042	40042	40042	40042	40042
160024	40041	299	1	1	6	1	90	25	240010	80010	160000	10	160000	50	1440000	0	40022	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	2	0	54	5021	10	16	15	16	40103	80962	0	80000	80010	40042	40529	40275	40438	40989
160024	41240	309	3	2	57	1	48	25	240010	80010	160000	10	160000	50	1440000	0	40022	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	213	5021	16	16	14	17	40038	80000	0	80000	80010	40042	40042	40042	40042	40042
160024	40041	300	1	1	0	1	48	25	240010	80010	160000	10	160000	50	1440000	1	40022	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	99	5021	16	16	17	17	40038	80000	0	80000	80010	40042	40042	40042	40042	40042
160024	40041	300	1	1	0	1	48	25	240010	80010	160000	10	160000	50	1440000	1	40022	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	135	5021	15	16	15	16	40038	80000	0	80000	80010	40042	40042	40042	40042	40042

FCVTNU (scalar, D to X)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations