Apple M1 Microarchitecture Research by Dougall Johnson

Firestorm: Overview | Base Instructions | SIMD and FP Instructions
Icestorm:  Overview | Base Instructions | SIMD and FP Instructions

FCVTNU (scalar, H to W)

Test 1: uops

Code:

  fcvtnu w0, h0
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 3.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 2.000

retire (01)cycle (02)031e1f3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch fp/simd (57)huge thing fp/simd (5b)696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op fp/simd (7e)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst integer (97)a8accfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
2004541400432530001000200020001800052254154124832742000200020005415411110011000007321622538100010001000542542542542542
2004541400432530001000200020001800052254154124832742000200020005415411110011000037321622538100010001000542542542542542
2004541400432530001000200020001800052254154124832742000200020005415411110011000007321622538100010001000542542542542542
2004541400432530001000200020001800052254154124832742000200020005415411110011000007321622538100010001000542542542542542
20045415120432530001000200020001800052254154124832742000200020005415411110011000007321622538100010001000542542542542542
2004541400432530001000200020001800052254154124832742000200020005415411110011000007321622538100010001000542542542542542
2004541400432530001000200020001800052254154124832742000200020005415411110011000007321622538100010001000542542542542542
2004541400432530001000200020001800052254154124832742000200020005415411110011000007321622538100010001000542542542542542
2004541400432530001000200020001800052254154124832742000200020005415411110011000007321622538100010001000542542542542542
2004541400482530001000200020001800052254154124832742000200020005415411110011000007321622538100010001000542542542542542

Test 2: Latency 1->2 roundtrip

Code:

  fcvtnu w0, h0
  fmov d0, x0
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 13.0038

retire (01)cycle (02)030b18191e1f3f4f51inst issue (52)~issue int (53)~issue fp/simd (54)~issue ld/st (55)~dispatch int (56)~dispatch fp/simd (57)~dispatch ld/st (58)huge thing int (59)huge thing ld/st (5a)huge thing fp/simd (5b)6061696b6d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op ld/st (7d)~map op fp/simd (7e)~map lookup int (7f)~map lookup ld/st (80)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa0a6a7a8a9acc2cdcfd0d5d6ddinst fetch restart (de)e0? int output thing (e9)ld/st retires (ed)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
302041300389740000013002311941725401001010020000100001002000010000500621497914801034131300130130038130038125476312624630100200100002000020010000201301300381300381120201100991001010010000100010000000000131033162212952510000100001000010100130040130387130039130039130039
302041300389740000013002311941725401001010020000100001002000010000500621497914801034011300130130038130038125476312624630100200100002000020010000200001300381300381120201100991001010010000100010000000000131022162212952510000100001000010100130039130039130039130039130039
3020413003897400012013002311941725401001011020000100001002000010000500621497914801034101300130130038130038125476312624630100200100002000020010000200001300381300381120201100991001010010000100010000000000131012162212952510000100001000010100130039130039130039130039130039
302041300389740000013002311941725401001010020000100001002000010000500621497914801034101300130130038130038125476312624630100200100002000020010000200001300381300381120201100991001010010000100010000000000131012162212952510000100001000010100130039130039130039130039130039
302041300389740000013002811941725401001010020000100001002000010000500621497914801034101300130130038130038125476312624630100200100002000020010000200001300381300381120201100991001010010000100010000000000131012162212952510000100001000010100130039130039130039130039130039
302041300409740000013002311941725401001010020000100001002000010000500621497914801034001300130130038130038125476312624630100200100002000020010000200001300381300381120201100991001010010000100010000000000131012162212952510000100001000010100130039130039130039130039130039
302041300419750000013002311941725401001010020000100001002000010000500621497914801034101300130130038130038125476312624630100200100002000020010000200001300381300381120201100991001010010000100010000000000131012163212952510000100001000010100130039130039130039130045130039
302041300389740000013002311941525401001010020000100001002000010000500621497914801034101300130130038130038125476312624630100200100002000020010000200001300381300381120201100991001010010000100010000000000131012162212952510000100001000010100130039130039130039130039130039
302041300389740000013002311941725401001010020000100001002000010000500621497914801034101300130130038130038125476312624630100200100002000020010000200001300381300381120201100991001010010000100010000000000131013162312952510000100001000010100130039130039130039130039130039
302041300389740000013002311941725401001010020000100001002000010000500621497914801034101300130130038130038125476312624630100200100002000020010000200001300381300381120201100991001010010000100010000000000131012162212952510000100001000010100130039130039130039130039130039

1000 unrolls and 10 iterations

Result (median cycles for code): 13.0038

retire (01)cycle (02)030b18191e3f4f51inst issue (52)~issue int (53)~issue fp/simd (54)~issue ld/st (55)~dispatch int (56)~dispatch fp/simd (57)~dispatch ld/st (58)huge thing int (59)huge thing ld/st (5a)huge thing fp/simd (5b)60696b6d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op ld/st (7d)~map op fp/simd (7e)~map lookup int (7f)~map lookup ld/st (80)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa0a1a6a8a9acb6branch mispredict (cb)cdcfd2d5d6ddinst fetch restart (de)e0? int output thing (e9)ld/st retires (ed)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
300241300389740000130023119417254001010010200001000010200001000050621517114800025113001301300381300381254983126268300102010000200002010000200001300381300381120021109101001010000100010000000000127001161112952510000100001000010010130039130039130039130039130039
300241300389740000130023119417254001010010200001000010200001000050621795514800361113001301300381300381254983126268300102010000200002010000200001300381300381120021109101001010000100010000000000127001161112952510000100001000010010130039130039130039130039130039
300241300389740000130023119417254001010010200001000010200001000050621910714800592113001301300381300381254983126268300102010000200002010000200001300381300381120021109101001010000100010000300000127001161112952510000100001000010010130039130039130039130039130040
300241300389740000130023119417254001010010200001000010200001000050621670714800025113001301300381300381254983126268300102010000200002010000200001300381300381120021109101001010000100010000000000127001161112952510000100001000010010130039130039130039130039130039
300241300389740009130023119417254001010010200001000010200001000050621641914800025113001301300381300681254983126268300102010000200002010000200001300381300381120021109101001010000100010000000000127001161112958010000100001000010010130039130039130039130039130039
300241300389740000130023119417254001010010200001000010201261000050621526714800025113001301300381300381254983126268300102010000200002010000200001300381300421120021109101001010000100010000000000127001161112952510000100001000010010130039130039130039130039130039
300241300389740000130023119417254001010010200001000010200001000050621862714800249113001301300381300381254983126268300102010000200002010000200001300381300381120021109101001010000100010000000000127001161112952510000100001000010010130039130039130039130039130039
300241300389740000130023119417254001010010200001000010200001000050621733114800025113001301300381300381254983126268300102010000200002010000200001300381300381120022109101001010000100010000006000127001161112952510000100001000010010130039130039130039130039130039
300241300389740000130023119417254001010010200001000010200001000050621790714800248113001301300381300381254983126268300102010000200002010000200001300381300382120021109101001010000100010000000000127001161112952510000100001000010010130039130039130039130039130039
300241300389740000130023119417254001010010200001000010200001000050621992314800025113001301300381300381254983126268300102010000200002010000200001300381300381120021109101001010000100010000000000127001161112952510000100001000010010130039130039130039130039130039

Test 3: throughput

Count: 8

Code:

  fcvtnu w0, h8
  fcvtnu w1, h8
  fcvtnu w2, h8
  fcvtnu w3, h8
  fcvtnu w4, h8
  fcvtnu w5, h8
  fcvtnu w6, h8
  fcvtnu w7, h8
  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

retire (01)cycle (02)030a0b18191e1f3a3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)9fa0a1a6a8a9acc2c5branch mispredict (cb)cdcfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
1602044004131100000003225240104801001600041001600205001440132040022400414004119977619992160120200160032200160032400414004111802011009910080100100000001380111511711600400388000080000801004004240042400424004240042
160204400413110000000322524010480100160004100160020500144013204002240041400411997761999216012020016003220016003240041400411180201100991008010010000000810111511701600400388000080000801004004240042400424004240042
160204400413100000000322524010480100160004100160020500144013214002240041400411997761999216012020016003220016003240041400411180201100991008010010000052030111511701600400388000080000801004004240042400424004240042
160204400413110000000322524010480100160004100160020500144013214002240041400411997761999216012020016003220016003240041400411180201100991008010010000039000111511701600400388000080000801004004240042400424004240042
16020440041310000000032252401048010016000410016002050014401320400224004140041199776199921601202001600322001600324004140041118020110099100801001000009030111511701610400388000080000801004004240042400424004240042
160204400413100000000322524010480100160004100160020500144013214002240041400411997761999216012020016003220016003240041400411180201100991008010010000039000111511701600400388000080000801004004240042400424004240042
160204400413100000000322524010480100160004100160020500144013214002240041400411997761999216012020016003220016003240041400411180201100991008010010000079030111511701600400388000080000801004004240042400424004240042
160204400413100000000322524010480100160004100160020500144013214002240041400411997761999216012020016003220016003240041400411180201100991008010010000067090111511701600400388000080000801004004240042400424004240042
160204400413100000000882524010480100160004100160020500144184504002240041400411997761999216012020016003220016003240041400411180201100991008010010000045030111511701600400388000080000801004004240042400424004240042
16020440041310000000032252401048010016000410016002050014401321400224004140041199776199921601202001600322001600324004140041118020110099100801001000000030111511701600400388000080000801004004240042400424004240042

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

retire (01)cycle (02)031e3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)9fa0a1a8accfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
1600244005530069422524001080010160000101600005014400000400224004140041199963200211600102016000020160000400414004111800211091080010100000502031653400388000080000800104004240042400424004240042
160024400413000422524001080010160000101600005014400000400224004140041199963200211600102016000020160000400414004111800211091080010100000502021655400388000080000800104004240042400424004240042
160024400413000422524001080010160000101600005014400001400224004140041200213200211600102016000020160000400414004111800211091080010100200502051665400388000080000800104004240042400424004240042
1600244004129939422524001080010160000101600005014400001400224004140041199963200211600102016000020160000400414004111800211091080010100080502061656400388000080000800104004240042400424004240042
160024400413000422524001080010160000101600005014400001400224004140041199963200211600102016000020160000400414004111800211091080010100000502051632400388000080000800104004240042400424004240042
160024400413000422524001080010160000101600005014400001400224004140041199963200211600102016000020160000400414004111800211091080010100000502061656400388000080000800104004240042400424004240042
1600244004130048422524001080010160000101600005014400000400224004140041199963200211600102016000020160000400414004111800211091080010100000502021653400388000080000800104004240042400424004240042
160024400413000422524001080010160000101600005014400000400224004140041200923200211600102016000020160000400414004111800211091080010100000502031623400388000080000800104004240042400424004240042
16002440041301452532524001080010160000101600005014400000400224004140041199963200211600102016000020160000400414004111800211091080010100000502021623400388000080000800104004240042400424004240042
160024400413000422524001080010160000101600005014400001400224004140041199963200211600102016000020160000400414004111800211091080010100000502021655400388000080000800104004240042400424004240042