Apple M1 Microarchitecture Research by Dougall Johnson

Firestorm: Overview | Base Instructions | SIMD and FP Instructions
Icestorm:  Overview | Base Instructions | SIMD and FP Instructions

FCVTNU (scalar, H to X)

Test 1: uops

Code:

  fcvtnu x0, h0
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 3.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 2.000

retire (01)cycle (02)031e3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch fp/simd (57)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op fp/simd (7e)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst integer (97)a8a9accfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
20045414043253000100020002000180000522541541248327420002000200054154111100110000007311611538100010001000542542542542542
20045414043253000100020002000180000522541541248327420002000200054154111100110000007311611538100010001000542542542542542
20045414043253000100020002000180001522541541248327420002000200054154111100110000007311611538100010001000542542542542542
20045414043253000100020002000180001522541541248327420002000200054154111100110000007311611538100010001000542542542542542
20045414043253000100020002000180000522541541248327420002000200054154121100110000007311611538100010001000542542542542542
20045414043253000100020002000180000522541541248327420002000200054154111100110000007311611538100010001000542542542542542
20045414343253000100020002000180001522541541248327420002000200054154111100110000067311611538100010001000542542542542542
20045414043253000100020002000180001522541541248327420002000200054154111100110000007311611538100010001000542542542542542
20045414043253000100020002000180001522541541248327420002000200054154111100110000007311611538100010001000542542542542542
20045414043253000100020002000180000522541541248327420002000200054154111100110000007311611538100010001000542542542542542

Test 2: Latency 1->2 roundtrip

Code:

  fcvtnu x0, h0
  fmov d0, x0
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 13.0038

retire (01)cycle (02)03080b18191e1f3f4f51inst issue (52)~issue int (53)~issue fp/simd (54)~issue ld/st (55)~dispatch int (56)~dispatch fp/simd (57)~dispatch ld/st (58)huge thing int (59)huge thing ld/st (5a)huge thing fp/simd (5b)60696b6d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op ld/st (7d)~map op fp/simd (7e)~map lookup int (7f)~map lookup ld/st (80)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa0a1a6a8a9acc2c5cfd0d5d6ddinst fetch restart (de)e0? int output thing (e9)ld/st retires (ed)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
302041300389740000001300231194172540100101002000010000100200001000050062149791480103401300130130038130038125476312624630100200100002000020010000200001300381300381120201100991001010010000100001000000000131012162212952510000100001000010100130039130039130039130039130039
302041300389740000901300231194172540100101002000010000100200001000050062149791480103401300130130038130038125476312624630100200100002000020010000200001300381300381120201100991001010010000100001000000020131013162212974310000100001000010100130039130039130039130040130039
3020413003897400001201300231194172540100101002000010000100200001000050062149791480103401300130130038130038125476312624630100200100002000020010000200001300381300391120201100991001010010000100001000000300131012162212952510000100001000010100130287130039130042130039130039
302041300409740000001300251195972540100101002000010000100200001000050062151231480250901300160130048130043125476312624630100200100002000020010000200001300381300381120201100991001010010000100001000000600131012162212952510000100001000010100130039130039130039130039130039
302041300389770000001300231194172540100101002000010000100200001000050062149791480103401300130130038130038125476312624630100200100002000020010000200001300381300381120201100991001010010000100001000000000131012162212952510000100001000010100130039130039130039130039130039
302041300389740000001300231194272540100101002000010000100200001000050062149791480103401300130130038130038125476312624630100200100002000020010000200001300381300381120201100991001010010000100001000000000131012162212953110000100001000010100130039130039130039130039130039
302041300389730000001300231194172540100101002000010000100200001000050062149791480103401300130130038130038125476312624630100200100002000020010000200001300381300381120201100991001010010000100001000000000131012162212952510000100001000010100130075130039130039130039130039
3020513003897400008101300231194172540100101002000010000100200001000050062149791480103401300130130038130038125476312624630100200100002000020010000200001300381300381120201100991001010010000100001000000000131013162212952510003100001000010100130039130039130039130039130039
302041300389740000001300231194172540100101002000010000100200001000050062149791480103401300130130038130038125476312624630100200100002000020010000200001300381300381120201100991001010010000100001000000000131012162212952510000100001000010100130039130039130039130039130039
302041300389740000001300231194172540100101002000010000100200001000050062149791480103401300130130038130038125476312624630100200100002000020010000200001300381300381120201100991001010010000100001000000000131012162212952510000100001000010100130039130039130039130039130039

1000 unrolls and 10 iterations

Result (median cycles for code): 13.0038

retire (01)cycle (02)0304080a0b18191e1f3a3f4f51inst issue (52)~issue int (53)~issue fp/simd (54)~issue ld/st (55)~dispatch int (56)~dispatch fp/simd (57)~dispatch ld/st (58)huge thing int (59)huge thing ld/st (5a)huge thing fp/simd (5b)60696b6d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op ld/st (7d)~map op fp/simd (7e)~map lookup int (7f)~map lookup ld/st (80)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa0a1a6a7a8acc2c5cfd5d6ddinst fetch restart (de)e0? int output thing (e9)ld/st retires (ed)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
300241300389740000009001300231194172540010100102000010000102000010000506214979148000251130013013003813003812549831262683001020100002000020100002000013003813003811200211091010010100001000100000000012701162212952510000100001000010010130039130039130213130039130039
30024130038974000000000130023119419135402061005120079100631423134116668762825321497387601323140132741132447126626194127672346392412080241212412083234011329271328573012002110910100101000010001000001340160413162213002510000100001000010010132745132997134269133316133196
3002413410910361011424259403432113270511953119040060100152002610000112069810735876214979149550041132228013350313272412687131262683001020100002000020100002000013003813003811200211091010010100001000100000000012702161112952510000100001000010010130039130039130039130039130039
300241300389740000000001300231194172540010100102000010000102000010000506214979148000250130013013003813003812549831262683001020100002000020100002000013003813003811200211091010010100001000100000000012703161212952510000100001000010235130081130106130046130039130039
3002413003897400000012001300231194172540010100102000010000102000010000506214979148000250130013013003813003812549831262683001020100002000020100002000013003813003811200211091010010100001000100000000012703163212952510000100001000010010130039130039130039130039130039
300241300389740000000001300231194172540010100102000010000102000010000506214979148000250130014013003813003812549831262683001020100002000020100002000013003813003811200211091010010100001000100000000012703162312952510000100001000010010130039130039130039130039130039
300241300389740000000001300231194172540010100102000010000102000010000506214979148000250130013013003813003812549831262683001020100002000020100002000013003813003811200211091010010100001000100000000012703163212952610000100001000010010130075130039130039130092130039
300241300389890000000001301101194172540010100102000010000102000010000506214979148000250130013013003813003812549831262683001020100002000020100002000013003813003811200211091010010100001000100000000012703163212952510000100001000010010130039130039130039130039130039
300241300389740000000001300231194562540010100102000010000102000010000506214979148009580130013013003813004112549831262683001020100002000020100002000013003813003811200211091010010100001000100000000012702162212952510000100001000010010130039130039130039130039130039
300241300389740000000001300231194172540010100102000010000102000010000506214979148000250130013013003813003812549831262683001020100002000020100002000013003813003811200211091010010100001000100000000012702162212952510000100001000010010130039130039130041130039130040

Test 3: throughput

Count: 8

Code:

  fcvtnu x0, h8
  fcvtnu x1, h8
  fcvtnu x2, h8
  fcvtnu x3, h8
  fcvtnu x4, h8
  fcvtnu x5, h8
  fcvtnu x6, h8
  fcvtnu x7, h8
  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

retire (01)cycle (02)0308191e3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)9fa8acc5branch mispredict (cb)cdcfd5d6inst fetch restart (de)e0? int output thing (e9)eb? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
160204400663100003225240104801001600041001600205001440132040022400414004119977619992160120200160032200160032400414004111802011009910080100100653111511711604003880000080000801004004240042400424004240042
16020440041310000322524010480100160004100160020500144013204002240041400411997761999216012020016003220016003240041400411180201100991008010010003111511701604003880000080000801004004240042400424004240042
160204400413210003225240104801001600041001600205001440132040022400414004119977619992160120200160032200160032400414004111802011009910080100100320111511701604003880000080000801004004240042400424004240042
160204400413100003225240104801001600041001600205001440132040022400414004119977619992160120200160032200160032400414004111802011009910080100100380111511701604003880000080000801004004240042400424004240042
160204400413100003225240104801001600041001600205001440132040022400414004119977619992160120200160032200160032400414004111802011009910080100100440111511701604003880000080000801004004240042400424004240042
16020440041310000322524010480100160004100160020500144013204002240041400411997761999216012020016003220016003240041400411180201100991008010010076111511701604003880000080000801004004240042400424004240042
1602044004131000369725240104801001600041001600205001440132040022400414004119977619992160120200160032200160032400414004111802011009910080100100380111511701604003880000080000801004004240042400424004240042
160204400413110003225240104801001600041001600205001440132040022400414004119977619992160120200160032200160032400414004111802011009910080100100590111511701604003880000080000801004004240042400424004240042
160204400413100003225240104801001600041001600205001440132040022400414004119977619992160120200160032200160032400414004111802011009910080100100540111511701604003880000080000801004004240042400424004240042
16020440041311000322524010480100160004100160020500144013204002240041400411997761999216012020016003220016003240041400411180201100991008010010093111513201604003880000080000801004004240042400424004240042

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

retire (01)cycle (02)0307080b18191e1f3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)5f6061696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)9fa6a7a8a9acc2cfd2d5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
1600244005531000000120126252400108001016000010160000501440000000400224004140041199963200211600102016000020160000400414004111800211091080010100000005020012161516400388000080000800104004240042400424004240042
160024400413100000000422524001080010160000101600005014400000004002240041400411999634200211600102016000020160000400414004111800211091080010100030005020016161512400388000080000800104004240042400424004240042
160024400413100000024042252400108001016000010160000501440000000400224004140041199963200711600102016000020160000400414004111800211091080010100000005020013161311400388000080000800104004240042400424004240042
16002440041310000006042252408688001016000010160000501440000005400224004140041199963200211600102016000020160000400414004111800211091080010100010305020015161310400388000080000800104004240042400424004240042
160024400413100000000707252400108001016000010160000501443542105400224004140041199963200211600102016000020160000400414004111800211091080010100000005020013161415400388000080000800104004240042400424004240042
16002440041311000000084252400108001016000010160000501440000000400224004140041199963200211600102016000020160000400414004111800211091080010100040305020015161313400388000080000800104004240361400424004240042
160024400413100000000422524001080010160000101600005014400000004002240041400411999632200211600102016000020160000400414004111800211091080010100000005020011161613400388000080000800104004240042400424004240042
16002440041310000010042252400108001016000010160000501447000000400224004140041199963200211600102016000020160000400414004111800211091080010100000005020012161314400388000080000800104004240042400424004240042
160024400413100000012042252400108001016000010160000501440000000400224004140041199963200211600102016000020160000400414004111800211091080010100000005020017161215400388000080000800104004240042400424004240042
16002440041310000000042252400108001016000010160000501440000000400224004140041199963200211600102016000020160000400414004111800211091080010100000005020013161415400388000080000800104004240042400424004240042