Apple M1 Microarchitecture Research by Dougall Johnson

Firestorm: Overview | Base Instructions | SIMD and FP Instructions
Icestorm:  Overview | Base Instructions | SIMD and FP Instructions

FCVTNU (scalar, S to W)

Test 1: uops

Code:

  fcvtnu w0, s0
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 3.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 2.000

retire (01)cycle (02)03091e1f3a3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch fp/simd (57)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op fp/simd (7e)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst integer (97)a0a1a8acc2cfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
2004541400014325330410002000200018000152254154124832742000220820005415411110011000200007311611538100010001000542542542542542
20045414000012525300010002000200018000052254154124832742000200020005415411110011000000007311611538100010001000542542542542542
2004541400004325300010002000200018000152254154124832742000200020005415411110011000000009011611538100010001000542542542542542
20045414108804325300010002000200019900152254154124832742000200020005415411110011000000007311611538100010001000542542542542542
200454140132004325300010002000200018000052254154124832742000200020005415411110011000020027311611538100010001000542542542542542
2004541400004325300010002000200018000052254154124832742000200020005415411110011000000007311611538100010001000542542542542542
2004541400004325300010002000200018000052254154124832742000200020005415411110011000000007311611538100010001000542542542542542
2004541400004325300010002000200018000052254154124832742000200020005415411110011000001007311611538100010001000542542542542542
2004541400004357300010002000200018000052254154124832742000200020005415411110011000000007311611538100010001000542542542542542
2004541400004325300010002000200018000052254154124832742000200020005415411110011000000007311611538100010001000542542542542542

Test 2: Latency 1->2 roundtrip

Code:

  fcvtnu w0, s0
  fmov d0, x0
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 13.0038

retire (01)cycle (02)03080b181e3f4f51inst issue (52)~issue int (53)~issue fp/simd (54)~issue ld/st (55)~dispatch int (56)~dispatch fp/simd (57)~dispatch ld/st (58)huge thing int (59)huge thing ld/st (5a)huge thing fp/simd (5b)696b6d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op ld/st (7d)~map op fp/simd (7e)~map lookup int (7f)~map lookup ld/st (80)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa0a1a6a8accdcfd0d5d6ddinst fetch restart (de)e0? int output thing (e9)ld/st retires (ed)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
3020413003897400001300231194172540100101002000010000100200001000050062149791480103413001301300381300381254763126246301002001000020000200100002000013003813003811202011009910010100100001000010000000131012162212952510000100001000010100130039130039130039130039130039
3020413003897400001300231194172540100101002000010000100200001000050062149791480103413001301300381300381254763126246301002001000020000200100002012813003813003811202011009910010100100001000010000000131002162212952510000100001000010100130039130039130039130039130039
30204130038974000301300231194172540100101002000010000100200001000050062149791480103413001331300381300381254763126246301002001000020000200100002000013003813003811202011009910010100100001000010000000131012162212952510000100001000010100130039130039130039130075130039
3020413003897400091300231194172540100101002000410000100200001000050062149791480103413001301300381300381254763126246301002001000020000200100002000013003813003811202011009910010100100001000010000000131012162212952510000100001000010100130039130039130041130039130039
3020513010097400001300231194172540100101002000010000100200001000050062149791480103413001301300381300381254763126246301002001006320000200100002000013003813003811202011009910010100100001000010000000131012162212952510000100001000010100130039130039130039130039130039
3020413003897400001300231194172540100101002000010000100200001000050062149791480103413001301300381300381254763126246301002001000020000200100002000013003813003811202011009910010100100001000010000000131012162212952510000100001000010100130039130039130039130039130039
3020413003897400001300231196994740100101042000010000100201161000050062149791483527513001301300381300381254769126246301002001000020120202100002024113003813003811202011009910010100100001000010000000131012162212952510000100001000010100130039130039130039130039130041
3020413003897400001300231194172540100101002000010000100200001000050062149791480103413001301300381300381254763126246301002001000020000200100002000013003813003811202011009910010100100001000010000000131012162212952510000100001000010100130039130039130039130039130039
3020413003897400001300231194172540100101002000010000100200001000050062149791480103413001301300381300381254763126246301002001000020000200100002000013003813003811202011009910010100100001000010000001131012162212952510000100001000010100130039130039130039130039130039
3020413003897400001300231194172540100101002000010000100200001000050062149791480103413001301300381300381254763126246301002001000020000200100002000013003813003811202011009910010100100001000010000000131012162212952610000100001000010100130039130039130039130039130039

1000 unrolls and 10 iterations

Result (median cycles for code): 13.0038

retire (01)cycle (02)0308191e1f3f4f51inst issue (52)~issue int (53)~issue fp/simd (54)~issue ld/st (55)~dispatch int (56)~dispatch fp/simd (57)~dispatch ld/st (58)huge thing int (59)huge thing ld/st (5a)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op ld/st (7d)~map op fp/simd (7e)~map lookup int (7f)~map lookup ld/st (80)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa0a6a8acc2cfd5d6ddinst fetch restart (de)e0? int output thing (e9)ld/st retires (ed)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
300241300389800000130023119417254001010013200001000010200001000050621497914800025113009213003813003812549831262683001020100002000020100002000013003813003811200211091010010100001001000033012702161112952510000100001000010010130039130039130039130039130039
300241300389740000130023119417254001010010200001000010200001000050621497914800025113006213003813003812549831262683001020100002000020100002000013003813003811200211091010010100001001000000012702161112952510000100001000010010130039130039130071130039130039
300241300389740000130067119417254001010010200001000010200001000050621497914800025113005513003813003812549831262683001020100002000020100002000013003813003811200211091010010100001001000000012701161112952510000100001000010010130039130042130039130039130039
300241300389740000130023119417254001010010200001000010200001000050621497914800025113005013003813003812549831262683001020100002000020100002000013003813003811200211091010010100001001000000012701161112952510000100001000010010130039130039130039130039130039
300241300389740000130023119417254001010010200001000010200001000050621497914800025113005913003813003812549831262683001020100002000020100002000013003813003811200211091010010100001001000000012700161112952510000100001000010010130039130039130039130039130039
300241300389740000130023119417254001010012200001000010200001000050621497914800136113006713003813003812549831262683001020100002000020100002000013003813003811200211091010010100001001000000012701161112952510000100001000010010130039130039130039130039130039
300241300389740000130023119417254001010010200001000010200001000050621497914800025113006513003813003812549831262683001020100002000020100002000013003813003821200211091010010100001001000000012701161112952510000100001000010010130039130039130039130039130039
300241300389740000130023119417254001010010200001000010200001000050621497914800025113005913006913003812550431262683001020100002000020100002000013003813003811200211091010010100001001000000012701161012952510000100001000010010130039130039130039130039130039
300241300389740000130023119417254001010010200001000010201261000050621755714800139113001313004213003812549831262683001020100002000020100002000013003813003811200211091010010100001001000000012701161112952510000100001000010010130039130039130039130039130039
300241300389740000130023119417254001010010200001000010200001000050621497914800025113007513003813003812549831262683001020100002000020100002000013003813003811200211091010010100001001000010012702161212952510000100001000010010130039130039130039130039130039

Test 3: throughput

Count: 8

Code:

  fcvtnu w0, s8
  fcvtnu w1, s8
  fcvtnu w2, s8
  fcvtnu w3, s8
  fcvtnu w4, s8
  fcvtnu w5, s8
  fcvtnu w6, s8
  fcvtnu w7, s8
  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

retire (01)cycle (02)0307080a18191e1f3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)9fa0a1a6a8a9acc2c5branch mispredict (cb)cdcfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
16020440041311101000032252401048010016000410016002050014401321400224004140041199776199921601202001600322001600324004140041118020110099100801001000000000111511721611400388000080000801004004240042400424004240042
16020440041310101000032252401048010016000410016002050014401321400224004140041199776199921601202001600322001600324004140041118020110099100801001000000000111511711611400388000080000801004004240042400424004240042
16020440041311101000032252401048010016000410016002050014401321400224004140041199776199921601202001600322001600324004140041118020110099100801001000000030111511711611400388000080000801004004240042400424004240042
16020440041311101000032252401048010016000410016002050014401321400224004140041199776199921601202001600322001600324004140041118020110099100801001000000000111511711611400388000080000801004004240042400424004240042
16020440041310101000035252401048010016000410016002050014401321400224004140041199776199921601202001600322001600324004140041118020110099100801001000000000111511711611400388000080000801004004240042400424004240042
16020440041311101000032252401048010016000410016002050014401321400224004140041199776199921601202001600322001600324004140041118020110099100801001000000000111511711611400388000080000801004004240042400424004240042
16020440041310101000032252401048010016000410016002050014401321400224004140041199776199921601202001600322001600324004140041118020110099100801001000001000111511711611400388000080000801004004240042400424004240042
16020440041310101000032252401048010016000410016002050014401321400224004140041199776199921601202001600322001600324004140041118020110099100801001000000030111511711611400388000080000801004004240042400424004240042
1602044004131010191028279249303032441448136016234410616249856014612861407974099341051202389720526161776204161904206162840410004108014180201100991008010010022004688821115337112411400388000080000801004004240042401244004240042
160204400413101110013448868763192436388116416234810616143658414638761407894104240990202621282084116322420216333820216355840839413121718020110099100801001002222293460111511711611401028000080000801004050240597413904107240042

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

retire (01)cycle (02)0307080b181e3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696b6d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)9fa0a8acc5branch mispredict (cb)cdcfd5d6d9ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
1600244005430000000422524001080010160000101600005014400000400220400414004119996320021160010201600002016000040041400411180021109108001010000010502013160119400388000080000800104004240042400424004240042
160024400413000000274225240010800101600001016000050144000004002204004140041199963200211600102016000020160000400414004111800211091080010100000005020111601211400388000080000800104004240042400424004240042
160024400413000000070725240010800101600001016000050144000014002204004140041199963200211600102016000020160000400414004111800211091080010104000005020121601213400388000080000800104004240042400424004240042
16002440041300000004225240010800101600001016000050144000004002204004140041199963200211600102016000020160000400414004111800211091080010100030005020131601312400388000080000800104004240042401224012140204
160024400412990001010725240010800101600001016020850144000014002204004140041199963200211600102016000020160000400414004111800211091080010100000005020101601311400388000080000800104004240042400424004240042
16002440041300010004225240010800101600001016000050144000004002204004140041199963200211600102016000020160000400414004111800211091080010100000005020131601212400388000080000800104004240042400424004240042
16002440041300000004225240010800101601921016000050144000014002204004140041199963200211600102016000020160000400414004111800211091080010100100005020121601311400388000080000800104004240042400424004240042
160024400412990000184225241113800101600001016000050144000014002204004140041199963200211600102016000020160000400414004111800211091080010109000005020131601213400388000080000800104004240042400424004240042
1600244004130000021810725240010800101600001016000050144000004002204004140041199963200211600102016000020160000400414004111800211091080010100000005020121601210400388000080000800104012840042400424004240042
16002440041299000004225240010800101600001016000050144000014002204004140041199963200211600102016000020160000400414004121800211091080010100000005043121601210400388000080000800104004240042400424004240042