Firestorm: FCVTNU (scalar, S to W) measurements

Code:

  fcvtnu w0, s0

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 3.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 2.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	09	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
2004	541	4	0	0	0	1	43	25	3304	1000	2000	2000	18000	1	522	541	541	248	3	274	2000	2208	2000	541	541	1	1	1001	1000	2	0	0	0	0	73	1	16	1	1	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	0	0	0	125	25	3000	1000	2000	2000	18000	0	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	0	0	0	73	1	16	1	1	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	0	0	0	43	25	3000	1000	2000	2000	18000	1	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	0	0	0	90	1	16	1	1	538	1000	1000	1000	542	542	542	542	542
2004	541	4	1	0	88	0	43	25	3000	1000	2000	2000	19900	1	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	0	0	0	73	1	16	1	1	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	132	0	0	43	25	3000	1000	2000	2000	18000	0	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	2	0	0	2	73	1	16	1	1	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	0	0	0	43	25	3000	1000	2000	2000	18000	0	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	0	0	0	73	1	16	1	1	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	0	0	0	43	25	3000	1000	2000	2000	18000	0	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	0	0	0	73	1	16	1	1	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	0	0	0	43	25	3000	1000	2000	2000	18000	0	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	1	0	0	73	1	16	1	1	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	0	0	0	43	57	3000	1000	2000	2000	18000	0	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	0	0	0	73	1	16	1	1	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	0	0	0	43	25	3000	1000	2000	2000	18000	0	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	0	0	0	73	1	16	1	1	538	1000	1000	1000	542	542	542	542	542

Test 2: Latency 1->2 roundtrip

Code:

  fcvtnu w0, s0
  fmov d0, x0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 13.0038

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	1e	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30204	130038	974	0	0	0	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	130013	0	130038	130038	125476	3	126246	30100	200	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	1310	1	2	16	2	2	129525	10000	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	974	0	0	0	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	130013	0	130038	130038	125476	3	126246	30100	200	10000	20000	200	10000	20128	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	1310	0	2	16	2	2	129525	10000	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	974	0	0	0	30	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	130013	3	130038	130038	125476	3	126246	30100	200	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	1310	1	2	16	2	2	129525	10000	10000	10000	10100	130039	130039	130039	130075	130039
30204	130038	974	0	0	0	9	130023	119417	25	40100	10100	20004	10000	100	20000	10000	500	6214979	14801034	130013	0	130038	130038	125476	3	126246	30100	200	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	1310	1	2	16	2	2	129525	10000	10000	10000	10100	130039	130039	130041	130039	130039
30205	130100	974	0	0	0	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	130013	0	130038	130038	125476	3	126246	30100	200	10063	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	1310	1	2	16	2	2	129525	10000	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	974	0	0	0	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	130013	0	130038	130038	125476	3	126246	30100	200	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	1310	1	2	16	2	2	129525	10000	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	974	0	0	0	0	130023	119699	47	40100	10104	20000	10000	100	20116	10000	500	6214979	14835275	130013	0	130038	130038	125476	9	126246	30100	200	10000	20120	202	10000	20241	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	1310	1	2	16	2	2	129525	10000	10000	10000	10100	130039	130039	130039	130039	130041
30204	130038	974	0	0	0	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	130013	0	130038	130038	125476	3	126246	30100	200	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	1310	1	2	16	2	2	129525	10000	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	974	0	0	0	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	130013	0	130038	130038	125476	3	126246	30100	200	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	1	1310	1	2	16	2	2	129525	10000	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	974	0	0	0	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	130013	0	130038	130038	125476	3	126246	30100	200	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	1310	1	2	16	2	2	129526	10000	10000	10000	10100	130039	130039	130039	130039	130039

1000 unrolls and 10 iterations

Result (median cycles for code): 13.0038

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	19	1e	1f	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	ac	c2	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30024	130038	980	0	0	0	0	130023	119417	25	40010	10013	20000	10000	10	20000	10000	50	6214979	14800025	1	130092	130038	130038	125498	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	0	10000	3	3	0	1270	2	16	1	1	129525	10000	10000	10000	10010	130039	130039	130039	130039	130039
30024	130038	974	0	0	0	0	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	1	130062	130038	130038	125498	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	1270	2	16	1	1	129525	10000	10000	10000	10010	130039	130039	130071	130039	130039
30024	130038	974	0	0	0	0	130067	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	1	130055	130038	130038	125498	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	1270	1	16	1	1	129525	10000	10000	10000	10010	130039	130042	130039	130039	130039
30024	130038	974	0	0	0	0	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	1	130050	130038	130038	125498	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	1270	1	16	1	1	129525	10000	10000	10000	10010	130039	130039	130039	130039	130039
30024	130038	974	0	0	0	0	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	1	130059	130038	130038	125498	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	1270	0	16	1	1	129525	10000	10000	10000	10010	130039	130039	130039	130039	130039
30024	130038	974	0	0	0	0	130023	119417	25	40010	10012	20000	10000	10	20000	10000	50	6214979	14800136	1	130067	130038	130038	125498	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	1270	1	16	1	1	129525	10000	10000	10000	10010	130039	130039	130039	130039	130039
30024	130038	974	0	0	0	0	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	1	130065	130038	130038	125498	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	2	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	1270	1	16	1	1	129525	10000	10000	10000	10010	130039	130039	130039	130039	130039
30024	130038	974	0	0	0	0	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	1	130059	130069	130038	125504	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	1270	1	16	1	0	129525	10000	10000	10000	10010	130039	130039	130039	130039	130039
30024	130038	974	0	0	0	0	130023	119417	25	40010	10010	20000	10000	10	20126	10000	50	6217557	14800139	1	130013	130042	130038	125498	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	1270	1	16	1	1	129525	10000	10000	10000	10010	130039	130039	130039	130039	130039
30024	130038	974	0	0	0	0	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	1	130075	130038	130038	125498	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	0	10000	1	0	0	1270	2	16	1	2	129525	10000	10000	10000	10010	130039	130039	130039	130039	130039

Test 3: throughput

Count: 8

Code:

  fcvtnu w0, s8
  fcvtnu w1, s8
  fcvtnu w2, s8
  fcvtnu w3, s8
  fcvtnu w4, s8
  fcvtnu w5, s8
  fcvtnu w6, s8
  fcvtnu w7, s8

Initialization

  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss instruction (0a)	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	40041	311	1	0	1	0	0	0	0	32	25	240104	80100	160004	100	160020	500	1440132	1	40022	40041	40041	19977	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	1	1	1	5117	2	16	1	1	40038	80000	80000	80100	40042	40042	40042	40042	40042
160204	40041	310	1	0	1	0	0	0	0	32	25	240104	80100	160004	100	160020	500	1440132	1	40022	40041	40041	19977	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	1	1	1	5117	1	16	1	1	40038	80000	80000	80100	40042	40042	40042	40042	40042
160204	40041	311	1	0	1	0	0	0	0	32	25	240104	80100	160004	100	160020	500	1440132	1	40022	40041	40041	19977	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	0	0	0	3	0	1	1	1	5117	1	16	1	1	40038	80000	80000	80100	40042	40042	40042	40042	40042
160204	40041	311	1	0	1	0	0	0	0	32	25	240104	80100	160004	100	160020	500	1440132	1	40022	40041	40041	19977	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	1	1	1	5117	1	16	1	1	40038	80000	80000	80100	40042	40042	40042	40042	40042
160204	40041	310	1	0	1	0	0	0	0	35	25	240104	80100	160004	100	160020	500	1440132	1	40022	40041	40041	19977	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	1	1	1	5117	1	16	1	1	40038	80000	80000	80100	40042	40042	40042	40042	40042
160204	40041	311	1	0	1	0	0	0	0	32	25	240104	80100	160004	100	160020	500	1440132	1	40022	40041	40041	19977	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	1	1	1	5117	1	16	1	1	40038	80000	80000	80100	40042	40042	40042	40042	40042
160204	40041	310	1	0	1	0	0	0	0	32	25	240104	80100	160004	100	160020	500	1440132	1	40022	40041	40041	19977	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	0	1	0	0	0	1	1	1	5117	1	16	1	1	40038	80000	80000	80100	40042	40042	40042	40042	40042
160204	40041	310	1	0	1	0	0	0	0	32	25	240104	80100	160004	100	160020	500	1440132	1	40022	40041	40041	19977	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	0	0	0	3	0	1	1	1	5117	1	16	1	1	40038	80000	80000	80100	40042	40042	40042	40042	40042
160204	40041	310	1	0	1	9	10	282	792	4930	303	244144	81360	162344	106	162498	560	1461286	1	40797	40993	41051	20238	97	20526	161776	204	161904	206	162840	41000	41080	14	1	80201	100	99	100	80100	100	2	2	0	0	4	6888	2	1	1	1	5337	1	124	1	1	40038	80000	80000	80100	40042	40042	40124	40042	40042
160204	40041	310	1	1	1	0	0	1344	88	6876	319	243638	81164	162348	106	161436	584	1463876	1	40789	41042	40990	20262	128	20841	163224	202	163338	202	163558	40839	41312	17	1	80201	100	99	100	80100	100	2	2	2	2	2	9346	0	1	1	1	5117	1	16	1	1	40102	80000	80000	80100	40502	40597	41390	41072	40042

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	mmu table walk data (08)	l2 tlb miss data (0b)	18	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	d9	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	40054	300	0	0	0	0	0	42	25	240010	80010	160000	10	160000	50	1440000	0	40022	0	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	0	0	1	0	5020	13	16	0	11	9	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	300	0	0	0	0	27	42	25	240010	80010	160000	10	160000	50	1440000	0	40022	0	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	5020	11	16	0	12	11	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	300	0	0	0	0	0	707	25	240010	80010	160000	10	160000	50	1440000	1	40022	0	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	4	0	0	0	0	0	5020	12	16	0	12	13	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	300	0	0	0	0	0	42	25	240010	80010	160000	10	160000	50	1440000	0	40022	0	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	3	0	0	0	5020	13	16	0	13	12	40038	80000	80000	80010	40042	40042	40122	40121	40204
160024	40041	299	0	0	0	1	0	107	25	240010	80010	160000	10	160208	50	1440000	1	40022	0	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	5020	10	16	0	13	11	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	300	0	1	0	0	0	42	25	240010	80010	160000	10	160000	50	1440000	0	40022	0	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	5020	13	16	0	12	12	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	300	0	0	0	0	0	42	25	240010	80010	160192	10	160000	50	1440000	1	40022	0	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	1	0	0	0	0	5020	12	16	0	13	11	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	299	0	0	0	0	18	42	25	241113	80010	160000	10	160000	50	1440000	1	40022	0	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	9	0	0	0	0	0	5020	13	16	0	12	13	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	300	0	0	0	2	18	107	25	240010	80010	160000	10	160000	50	1440000	0	40022	0	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	5020	12	16	0	12	10	40038	80000	80000	80010	40128	40042	40042	40042	40042
160024	40041	299	0	0	0	0	0	42	25	240010	80010	160000	10	160000	50	1440000	1	40022	0	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	2	1	80021	10	9	10	80010	10	0	0	0	0	0	0	5043	12	16	0	12	10	40038	80000	80000	80010	40042	40042	40042	40042	40042

FCVTNU (scalar, S to W)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations