Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FCVTN (vector, 2D)

Test 1: uops

Code:

  fcvtn v0.2s, v0.2d
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100430372306125472510001000100039816003018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
100430372306125472510001000100039816013018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
100430372306125472510001000100039816013018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
100430372406125472510001000100039816003018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
100430372306125472510001000100039816003018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
100430372306125472510001000100039816003018303730372414328951000100010003037303711100110000073116122629100030383038303830383038
1004303723010325472510001000100039816013018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
100430372308925472510001000100039816013018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
100430372306125472510001000100039816003018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
100430372406125472510001000100039816003018303730372414328951000100010003037303711100110000373116112629100030383038303830383038

Test 2: Latency 1->2

Code:

  fcvtn v0.2s, v0.2d
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5e60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2c9cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eb? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020430037233000000061295472510100100100001001000050042771600030018300373003728264328745101002001000020010000300373003711102011009910010010000100000000009163661129982240100001003051530474304223046930468
1020430463237009412001056067122947498102211301007215310750680428628200301263026330467282884228814105662221116222010655304603021810110201100991001001000010000000000710125112963300100001003003830038300383003830038
1020430037232115466046006240295472510100100100001001000050042771600030018300373003728264328745101002201115620810665304653027591102011009910010010000100421042009500710116112963300100001003003830038300383013430038
102043008423300006006129547251010010010000100100005004277160003001830037300372826432874510100200100002001000030037300371110201100991001001000010000000300710116112963300100001003003830038300383003830038
1020430131235107326744006129547174101001001000013610900729428932800303423041830418282963828872107342261067122910988304683040821102011009910010010000100000000008083561229890230100001003032330135305133022730277
10204304192490100000416829493174101931441004814311200704428527200300183003730037282643287451026820010000200100003003730037111020110099100100100001000000000291710116112963300100001003003830038300863003830038
10204300372410000000822954725101001001000010010000500427716000300183003730037282643287451010020010000200100003003730037111020110099100100100001000121000000710116412963300100001003003830038300383003830038
102043003723200000006129547251010010010000100100005004277160103001830037300372826432874510100200100002001000030037300371110201100991001001000010000000020710116112963300100001003003830038300383003830038
102043003723300000006129547251010010010000100100005004277160003001830037300372826432874510100200100002001000030037300371110201100991001001000010000000000710116112963300100001003003830038300383003830038
102043003723200000006129547251010010010000100100005004277160003001830037300372826432874510100200100002001000030037300371110201100991001001000010000000000710116112963300100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03091e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024300372330210140429547251001010100001010000504277160130018300373003728286328767100102010000201000030037300371110021109101010000100006402162229629010000103003830038300383003830038
1002430037232006129547251001010100001010000504277160030018300373003728286328767100102010000201000030037300371110021109101010000100006402162229629010000103003830038300863022730038
1002430037233006129547251001010100001010000504277160130018300373003728286328767100102010000201000030037300371110021109101010000100006402162229629010000103003830038300383003830038
1002430037233006129547251001010100001010000504277160030018300373003728286328767100102010000201000030037300371110021109101010000100006402162229629010000103003830038300383003830038
1002430037232006129547251001010100001010000504277160130018300373003728286328767100102010000201000030037300371110021109101010000100006402162229629010000103003830038300383003830038
1002430037232036129547251001010100001010000504277160130018300373003728286328773100102010000201000030037300371110021109101010000100006402162229629010000103003830038300383003830038
100243003722502076129547251001010100001010000504277160130018300373003728286328767100102010000201000030037300375110021109101010000100006402162229629010000103003830038300383003830038
10024300372250246129547251001010100001010000504277160130018300373003728286328767100102010000201000030037300371110021109101010000100006402162229629010000103003830038300383003830038
1002430037225006129547251001010100001010000504277160130018300373003728286328767100102010000201000030037300371110021109101010000100006402162229629010000103003830038300383003830038
1002430037225006129547251001010100001010000504277160130018300373003728286328767100102010000201000030037300371110021109101010000100006402162229629010000103003830038300383003830038

Test 3: throughput

Count: 8

Code:

  fcvtn v0.2s, v8.2d
  fcvtn v1.2s, v8.2d
  fcvtn v2.2s, v8.2d
  fcvtn v3.2s, v8.2d
  fcvtn v4.2s, v8.2d
  fcvtn v5.2s, v8.2d
  fcvtn v6.2s, v8.2d
  fcvtn v7.2s, v8.2d
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0e2? simd retires (ee)? int retires (ef)f5f6f7f8fd
802042003915500030258010810080008100800205006401321200202003920039997769990801202008003220080032200392003911802011009910010080000100000111511801600200360800001002004020040200402004020040
8020420039155000116258010810080008100800205006401321200202003920039997769990801202008003220080032200392003911802011009910010080000100000111511801600200360800001002004920049200502004920049
802042004915510085278011610080016100800285006401961200292004820048997699986801282008003820080038200482004811802011009910010080000100100222512812311200450800001002025320049200492005020050
8020420049155000922780116100800161008002850064019602002920049200489976109986801282008003820080038202732003911802011009910010080000100100111511801600200360800001002004020040200402004020040
802042003915600030258010810080008100800205006401321200202003920039997769990801202008003220080032200392003911802011009910010080000100009111511801600200360800001002004020040200402004020040
802042003915500030258010810080008100800205006401321200202003920039997769990801202008003220080032200392003911802011009910010080000100003111511801600200360800001002004020040200402004020040
802042003915500030258010810080008100800205006401321200202003920039997769990801202008003220080032200392003911802011009910010080000100000111511801600200360800001002004020040200402004020040
802042003916500030258010810080008100800205006401321200202003920039997769990801202008003220080032200392003911802011009910010080000100000111511801600200360800001002004020040200402004020040
802042003915600030258010810080008100800205006401321200202003920039997769990801202008003220080032200392003911802011009910010080000100000111511801600200360800001002004020040200402004020040
8020420039155000302580108100800081008002050064013212009620039200399977699908012020080032200800322003920039118020110099100100800001001063111511801600200360800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)191e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8002420050156005740448010710800001080000506400000020020200392003999963100198001020800002080000200392003911800211091010800001000005020116112003680000102004020040200402004020040
80024200391551018828258001010800001080104506408281120020200392003999963100198001020800002080000200392003911800211091010800001000005020116112003680000102004020040200402004020040
800242003915601040258001010800001080212506400000020020200392003999963100198001020800002080000200392003911800211091010800001001005020116112003680000102004020040200402004020040
800242003916100040258001010800001080000506400000120020200392003999963100198001020800002080000200392003911800211091010800001000005020116112003680000102004020040200402004020040
80024200391550005017258001010800001080000506400000120020200392003999963100198001020800002080000200392003911800211091010800001000005020116112003680000102004020040200402004020040
800242003915600040258001010800001080000506400000120020200392003999963100198001020800002080000200392003911800211091010800001000005020116112003680000102004020040200402004020040
800242003915500040258001010800001080000506400000120020200392003999963100198001020800002080000200392003911800211091010800001000005020116112003680000102004020040200402004020040
80024200421560001032580010108000010802115064000001200592009020088100058100458001020800002080000200392003921800211091010800001000005020116112003680000102004020040200402004020040
800242003915500040258001010800001080000506400000120020200392003999963100198001020800002080000200392003911800211091010800001000005020116112003680000102004020040200402004020040
8002420039155000357258001010800001080000506400000120020200392003999963100198001020800002080000200392003911800211091010800001000305020116112003680000102004020040200402004020040