Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FCVTPS (scalar, D to D)

Test 1: uops

Code:

  fcvtps d0, d0
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03mmu table walk instruction (07)l2 tlb miss instruction (0a)1e3a3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10043037241102682547251000100010003981603018303730372414328951000100010003037303711100110000077516442629100030383038303830383038
10043037231102682547251000100010003981603018303730372414328951000100010003037303711100110000077416442629100030383038303830383038
10043037241102682547251000100010003981603018303730372414328951000100010003037303711100110002077416442629100030383038303830383038
10043037231102682547251000100010003981603018303730372414328951000100010003037303711100110003077416442629100030383038303830383038
10043037241102682547251000100010003981603018303730372414328951000100010003037303711100110000077416442629100030383038303830383038
10043037231102682547251000100010003981603018303730372414328951000100010003037303711100110000077416442629100030383038303830383038
100430372311242682547251000100010003981603018303730372414328951000100010003037303711100110000077416442629100030383038303830383038
10043037231102682547251000100010003981603018303730372414328951000100010003037303711100110000077416442629100030383038303830383038
100430372311021102547251000100010003981603018303730372414328951000100010003037303711100110001377416442629100030383038303830383038
10043037231102682547251000100010003981603018303730372414328951000100010003037303711100110000077416442629100030383038303830383038

Test 2: Latency 1->2

Code:

  fcvtps d0, d0
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204300372320000308229547251010010010000100100005004277160030018030037300372826832874510100200100002001000030037300371110201100991001001000010000000071011611296330100001003003830038300383003830038
102043003723200003011029547251010010010000100100005004277160030018030037300372826432874510100200100002001000030037300371110201100991001001000010000000071011611296520100001003003830038300383003830038
10204300372330000306129547251010010010000100100005004277160030018030037300372826432874510100200100002001000030037300371110201100991001001000010000003071011611296330100001003013630038300383003830038
10204300372330000144074729547441012010010000100100005004277160030018030037300372826432874510100200100002001000030037300371110201100991001001000010000013071011611296330100001003003830038300383003830038
10204300372320000308229547251010010010000100100005004277160030018030037300372826432874510100200100002001000030037300371110201100991001001000010000000071031611296330100001003003830038300383003830038
102043003723200003023729547251010010010000100100005004277160030018030037300372826432874510100200100002001000030037300371110201100991001001000010000006071011611296330100001003003830038300383003830038
10204300372330000308229547251010010010000100100005004277160030018030037300372826432874510100200100002001000030037300371110201100991001001000010000013071011611296330100001003003830038300383003830038
10204300372330000308229547251010010010000100100005004277160030018030037300372826432874510100200100002001000030037300371110201100991001001000010000000071011611296330100001003003830038300383003830038
10204300372330000420140295472510100100100001001000050042771600300180300373003728264328745101002001000020010000300373003711102011009910010010000100000139071011611296330100001003003830038300383003830038
1020430037233000012099029547251010010010000100100005004277160030018030037300372826432874510100200100002001000030037300371110201100991001001000010000000071011611296333100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)st unit uop (a7)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0eb? simd retires (ee)? int retires (ef)f5f6f7f8fd
100243003723300012006129538251001010100001010000504278512130018300373003728286328767100102010044201000030037300371110021109101010000100003006404165529629010000103003830038300383003830038
100243003723300012006129547251001010100001010000504277160130162300373003728286328767100102010000201000030037300371110021109101010000100001007325164429629010000103003830038300383003830038
1002430037232000132008229547431001010100001110000504277160130018300373003728286328767100102010000201000030037300371110021109101010000102201406406163529629010000103003830038300383003830038
100243003723200012006129547251001010100001010000504277160130018300373003728286328767103142010000201000030037300371110021109101010000100000006405165529629010000103003830038300383003830038
1002430037233000120010329529251001010100001010000504277160130018300373003728286328767100102010000201000030037300371110021109101010000100000006406166629629010000103003830038300383003830038
1002430037233010088084295472510010101000010100005042771600300183003730037282861128767100102010000201000030037300371110021109101010000100002006404165629629010000103003830038300383003830038
10024300372330000006129547251001010100001010000504277160130018300373003728286328767100102010492201000030037300371110021109101010000100000006406165629629010000103003830038300383007830038
10024300372330000006129547251001010100001010000504277160030018300373003728286328767100102010000201000030037300371110021109101010000100000006405165529629010000103003830038300383003830038
10024300372250003006129547251001010100001010000504277160030018300373003728286328767100102010000201000030037300371110021109101010000100000006405165429629010000103003830038300383003830038
100243003722500000044129547251001812100001010000504277160030018300373003728286328767100102010000201000030037300371110021109101010000100009006406166529629010000103003830038300383003830038

Test 3: throughput

Count: 8

Code:

  fcvtps d0, d8
  fcvtps d1, d8
  fcvtps d2, d8
  fcvtps d3, d8
  fcvtps d4, d8
  fcvtps d5, d8
  fcvtps d6, d8
  fcvtps d7, d8
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfmap dispatch bubble (d6)fetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420039155213025801081008000810080020500640132020020200392003999766999080120200800322008003220039200391180201100991001008000010000111511816020036800001002004020040200402004020040
8020420039155183025801081008000810080020500640132120020200392003999776999080120200800322008003220039200391180201100991001008000010000111511816020036800001002004020040200402004020040
8020420039155213025801081008000810080020500640132120020200392003999776999080120200800322008003220039200391180201100991001008000010000111511816020036800001002004020040200402004020040
8020420039155213025801081008000810080020500640132120020200392003999776999080120200800322008003220039200391180201100991001008000010000111511816020036800001002004020040200402004020040
8020420039155273025801081008000810080020500640132120020200392003999776999080120200800322008003220039200391180201100991001008000010000111511816020036800001002004020040200402004020040
802042003915603025801081008010810080020500640132120020200392003999776999080120200800322008003220039200391180201100991001008000010000111511816020036800001002004020040200402004020040
802042003915503025801081008000810080020500640132120020200392003999776999080120200800322008003220039200391180201100991001008000010000111511816020036800001002004020040200402004020040
8020420039155273025801081008000810080020500640132120020200392003999776999080120200800322008003220039200391180201100991001008000010000111511816020036800001002004020040200402004020040
802042003915503025801081008000810080020500640132120020200392003999776999080120200800322008003220039200391180201100991001008000010013111517316020036800001002004020040200402004020040
802042003915603025801081008000810080020500640132120020200392003999776999080120200800322008003220039200391180201100991001008000010000111511816020036800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03l1i tlb fill (04)mmu table walk instruction (07)l2 tlb miss data (0b)1e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8002420051155100040258001010800001080000506400000200202003920039999631001980010208000020800002003920039118002110910108000010005020316112003680000102004020040200402004020040
80024200391550004840258001010800001080000506400000200202003920039999631001980010208000020800002003920039118002110910108000010005020116112003680000102004020040200402004020040
80024200391550005440258001010800001080000506400000200202003920039999631001980010208000020800002003920039118002110910108000010005020116112003680000102004020040200402004020040
80024200391550004296258001010800001080000506400000200202003920039999631001980010208000020800002003920039118002110910108000010005054116112003680000102004020040200402004020040
8002420039155000040258001010800001080106506400000200202003920039999631001980010208000020800002003920039118002110910108000010005020116112003680000102004020040200402004020040
80024200391550001840258001010800001080000506400000200202003920039999631001980010208000020800002003920039118002110910108000010005020116112003680000102004020040200402004020040
80024200391550003940258001010800001080000506400000200202003920039999631001980010208000020800002003920039118002110910108000010005020116112003680000102004020040200402004020040
80024200391550003940258001010800001080000506400000200202003920039999631001980010208000020800002003920039118002110910108000010005020116112003680000102004020040200402004020040
8002420039155000040258001010800001080000506400000200202003920039999631001980010208000020800002003920039118002110910108000010005020116112003680000102004020040200402004020040
800242003915900014743258001010800001080000506400000200202003920039999631001980010208000020800002003920039118002110910108000010005020116112003680000102004020040200402004020040