Apple M1 Microarchitecture Research by Dougall Johnson

Firestorm: Overview | Base Instructions | SIMD and FP Instructions
Icestorm:  Overview | Base Instructions | SIMD and FP Instructions

FCVTPS (scalar, D to W)

Test 1: uops

Code:

  fcvtps w0, d0
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 3.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 2.000

retire (01)cycle (02)030b191e3a3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch fp/simd (57)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op fp/simd (7e)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst integer (97)a6a8a9acc2cfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
2004541500004325300010002000200018000052254154124832742000200020005415411110011000000007311611538100010001000542542542542542
2004541400004325300010002000200018000052254154124832742000200020005415411110011000000007311611538100010001000542542542542542
2004541400004325300010002000200018000052254154124832742000200020005415411110011000010007311611538100010001000542542542542542
2004541400004325300010002000200018000052254154124832742000200020005415411110011000000007311611538100010001000542542542542542
2004541400004325300010002000200018000052254154124832742000200020005415411110011000000007311611538100010001000542542542542542
2004541400004325300010002000200018000052254154124832742000200020005415411110011000000007311611538100010001000542542542542542
2004541400004325300010002000200018000052254154124832742000200020005415411110011000000007311611538100010001000542542542542542
2004541400004325300010002000200018000052254154124832742000200020005415411110011000000007311611538100010001000542542542542542
2004541400004325300010002000200018000052254154124832742000200020005415411110011000010007311611538100010001000542542542542542
2004541400004325300010002000200018000052254154124832742000200020005415411110011000000007311611538100010001000542542542542542

Test 2: Latency 1->2 roundtrip

Code:

  fcvtps w0, d0
  fmov d0, x0
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 13.0038

retire (01)cycle (02)030b0e18191e1f3a3f4f51inst issue (52)~issue int (53)~issue fp/simd (54)~issue ld/st (55)~dispatch int (56)~dispatch fp/simd (57)~dispatch ld/st (58)huge thing int (59)huge thing ld/st (5a)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op ld/st (7d)~map op fp/simd (7e)~map lookup int (7f)~map lookup ld/st (80)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa0a1a6a8a9acc2c5c8cdcfd0d5d6ddinst fetch restart (de)e0? int output thing (e9)ebld/st retires (ed)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
3020413037310080040000130032119417254010610118200001000010620000100005006214979148010341130013130038130038125476312630230769200100612000020410000200001300381300381120201100991001010010000100001001010001001310141622129525100000100001000010100130039130039130039130039130039
3020413003810080000000130023119418254010010100200001000010020000100005006214979148010340130013130038130038125476312624630100200100002000020010000200001300381300381120201100991001010010000100001000000000001310121622129525100000100001000010100130039130039130039130039130211
3020413003810080000000130023119417254010010100200001000010020000100005006214979148010340130013130038130038125476312624630100200100002000020010000200001303691300381120201100991001010010000100001000000900001310121622129525100000100001000010100130039130039130041130039130039
3020413004810110000000130023119417254010010109200001000010020000100005006214979148014790130013130038130380125476312624630100200100002000020010000200001300381300381120201100991001010010000100001000000000001310121622129527100000100001000010100130039130039130039130039130039
30204130038100700000001300231194172540129101002000010000100200001000064462149791480103411300131300381300381254762212624930100204100002000020010000200001300381300395120201100991001010010000100001000000000001310121622129525100000100001000010100130039130039130039130039130039
3020413003810080000001130023119417254010010100200001000210020000100005006214979148010340130013130038130038125476312624630100200100002000020010000200001300381300381120201100991001010010000100001000000000001310121622129558100000100001000010100130040130039130039130039130039
30204130038100802003935201300231194171104010010100200001000010020000100005006214979148010340130013130038130038125476312624630100200100002000020010000200001300381300381120201100991001010010000100001000000000001310121622129525100000100001000010100130039130039130039130039130039
3020413003810070000000130023119545254010010100200001000010020000100005006214979148010340130013130038130038125476312624630100200100002000020010000200001300381300381120201100991001010010000100001000000000001310125022129525100000100001000010100130373130039130039130039130039
3020413003810080000000130023119550254010010100200001000010020000100005006224986148013711130013130038130038125476312624630100200100002000020010122200001300381300381120201100991001010010000100001000000000001310121622129526100000100001000010100130039130039130039130039130039
302041300381008000057900130023119417254014010100200001000010020000100005006214979148010340130013130038130038125476312624630100200100002000020010000200001300381300381120201100991001010010000100001000000000001310121623129525100000100001000010100130039130039130039130041130039

1000 unrolls and 10 iterations

Result (median cycles for code): 13.0038

retire (01)cycle (02)03080b18191e1f3a3f4f51inst issue (52)~issue int (53)~issue fp/simd (54)~issue ld/st (55)~dispatch int (56)~dispatch fp/simd (57)~dispatch ld/st (58)huge thing int (59)huge thing ld/st (5a)huge thing fp/simd (5b)60696b6d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op ld/st (7d)~map op fp/simd (7e)~map lookup int (7f)~map lookup ld/st (80)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa1a6a7a8a9acc2branch mispredict (cb)cfd5d6ddinst fetch restart (de)e0? int output thing (e9)ld/st retires (ed)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
30024130039104500000001300231194172540010100102000010000102000010000506214979148000251130013013003913003812549831262683001020100002000020100002000013003813003811200211091010010100001001000000000012702161112952510000100001000010010130039130039130046130041130039
30024130038100811000001300231194172540010100102000010000102000010000506214979148000251130013013003813003812549831262683001020100002000020100002000013003813003811200211091010010100001001000000000012701161112952510000100001000010010130039130039130039130039130039
30024130038100700000001300231194172540010100102000010000102000010000506214979148000250130013013003813003812549831262683001020100002000020100002000013003813003811200211091010010100001001000005000012701161112952810000100001000010010130039130039130039130039130039
30024130038100800000001300231194172540010100102000010000102000010000506214979148000251130013013003813003812549831262683001020100002000020100002000013003813003811200211091010010100001001000000000012701161112952510000100001000010010130039130039130039130039130039
30025130038100800009001300231194172540022100102000010000102000010000506214979148000251130013013003813003812550231262683001020100002000020100002000013003813003811200211091010010100001001000000000012701161112952510000100001000010010130039130039130039130039130039
3002413003897400000001300231194172540010100102000010002102000010000506214979148000250130013013003813003812549831262683001020100002000020100002000013003813012611200211091010010100001001000000000012701162112933610000100001000010010130039130039130039130039130039
3002413003897400000001300231194172540010100102000010000102000010000506214979148000251130013013003813003812549831262683001020100002000020100002000013003813003811200211091010010100001001000000000012701161112952510000100001000010010130039130039130039130039130039
3002413003897400000001300231194172540010100102000010000102000010000506214979148000250130013013003813003812549831262683001020100002000020100002000013003813003811200211091010010100001001000000000012701161112952510000100001000010010130039130039130039130039130039
3002413003897400000001300231194172540010100102000010000102000010000506214979148000250130013013003813003812549831262683001020100002000020100002000013003913004111200211091010010100001001000000000012701161512956110001100001000010010130039130042130039130039130039
3002413004197401000001300231194172540010100102000010000102000010000506214979148000251130013013003813003812549831262683001020100002000020100002000013003813003811200211091010010100001001000413030012701161112952510000100001000010010130039130039130040130041130039

Test 3: throughput

Count: 8

Code:

  fcvtps w0, d8
  fcvtps w1, d8
  fcvtps w2, d8
  fcvtps w3, d8
  fcvtps w4, d8
  fcvtps w5, d8
  fcvtps w6, d8
  fcvtps w7, d8
  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

retire (01)cycle (02)030a0b0f1e3a3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696b6d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)9fa8acc5branch mispredict (cb)cdcfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
160204400633100001213425240104801001600041001600205001440132140022040041400411997761999216012020016003220016003240041400411180201100991008010010000111511891698400388000080000801004004240042400424004240042
16020440041310000013425240104801001600041001600205001440132040022040041400411997761999216012020016003220016003240041400411180201100991008010010003111511881689400388000080000801004004240042400424004240042
16020440041311000013425240104801001600041001600205001440132040022040041400411997761999216012020016003220016003240041400411180201100991008010010010111511881688400388000080000801004004240042400424004240042
16020440041311000016225240104801001600041001600205001440132140022040041400411997761999216012020016003220016003240041400411180201100991008010010000111511881689400388000080000801004004240042400424004240042
16020440041310000013225240104801001600041001600205001440132140022040041400411997761999216012020016003220016003240041400411180201100991008010010000111511861666400388000080000801004004240042400424004240042
16020440041310000013225240104801001600041001600205001440132140022040041400411997761999216012020016003220016003240041400411180201100991008010010000111511881688400388000080000801004004240042400424004240042
16020440041310000013225240104801001600041001600205001440132140022040041400411997761999216012020016003220016003240041400411180201100991008010010000111511881688400388000080000801004004240042400424004240042
16020440041311000013225240104801001600041001600205001440132140022040041400411997761999216012020016003220016003240041400411180201100991008010010000111511881688400388000080000801004004240042400424004240042
16020440041310000013225240104801001600041001600205001440132140022040041400411997761999216012020016003220016003240041400411180201100991008010010000111511881668400388000080000801004004240042400424004240042
16020440041310000013225240104801001600041001600205001440132140022040041400411997761999216012020016003220016003240041400411180201100991008010010000111511881683400388000080000801004004240042400424004240042

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

retire (01)cycle (02)031e3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696d6edispatch stall (70)74scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)9fa8accfd2icache miss (d3)d5d6daddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
16002440054310052252400108001016000010160000501440000140022400414004119996032002116001020160000201600004004140041118002110910800101000502000116011400388000080000800104004240042400424004240042
16002440041310042252400108001016000010160000501440000140022400414004119996032002116001020160000201600004004140041118002110910800101000502000116011400388000080000800104004240042400424004240042
16002440041310042252400108001016000010160000501440000040022400414004119996032002116001020160000201600004004140041118002110910800101000502000116011400388000080000800104004240042400424004240042
16002440041310042252400108001016000010160000501440000040022400414004119996032002116001020160000201600004004140041118002110910800101000502000116011400388000080000800104004240042400424004240042
16002440041310042252400108001016000010160000501440000140022400414004119996032002116001020160000201600004004140041118002110910800101000502000116011400388000080000800104004240042400424004240042
16002440041310042252400108001016000010160000501440000040022400414004119996032002116001020160000201600004004140041118002110910800101000502001116011400388000080000800104004240042400424004240042
16002440041310942252400108001016000010160000501440000040022400414004119996032002116001020160000201600004004140041118002110910800101010502000116011400388000080000800104004240042400424004240042
16002440041311042252400108001016000010160000501440000140022400414004119996032002116001020160000201600004004140041118002110910800101003502000116011400388000080000800104004240042400424004240042
16002440041310042252400108001016000010160000501440000140022400414004119996032002116001020160000201600004004140041118002110910800101000502000116011400388000080000800104004240042400424004240042
16002440041310042252400108001016000010160000501440000040022400414004119996032002116001020160000201600004004140041118002110910800101000502000116011400388000080000800104004240042400424004240042