Apple M1 Microarchitecture Research by Dougall Johnson

Firestorm: Overview | Base Instructions | SIMD and FP Instructions
Icestorm:  Overview | Base Instructions | SIMD and FP Instructions

FCVTPS (scalar, D to X)

Test 1: uops

Code:

  fcvtps x0, d0
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 3.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 2.000

retire (01)cycle (02)031e3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch fp/simd (57)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op fp/simd (7e)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst integer (97)a8accfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
2004541404325300010002000200018000152254154124832742000200020005415411110011000007311611538100010001000542542542542542
2004541404325300010002000200018000152254154124832742000200020005415411110011000107311611538100010001000542542542542542
2004541404325300010002000200018000052254154124832742000200020005415411110011000007311611538100010001000542542542542542
2004541404325300010002000200018000052254154124832742000200020005415411110011000007311611538100010001000542542542542542
2004541404325300010002000200018000052254154124832742000200020005415411110011000007311611538100010001000542542542542542
2004541404325300010002000200018000052254154124832742000200020005415411110011000007311611538100010001000542542542542542
2004541404325300010002000200018000152254154124832742000200020005415411110011000007311611538100010001000542542542542542
2004541404325300010002000200018000152254154124832742000200020005415411110011000007311611538100010001000542542542542542
2004541404325300010002000200018000052254154124832742000200020005415411110011000007311611538100010001000542542542542542
2004541404325300010002000200018000052254154124832742000200020005415411110011000007311611538100010001000542542542542542

Test 2: Latency 1->2 roundtrip

Code:

  fcvtps x0, d0
  fmov d0, x0
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 13.0038

retire (01)cycle (02)031e3f4f51inst issue (52)~issue int (53)~issue fp/simd (54)~issue ld/st (55)~dispatch int (56)~dispatch fp/simd (57)~dispatch ld/st (58)huge thing int (59)huge thing ld/st (5a)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op ld/st (7d)~map op fp/simd (7e)~map lookup int (7f)~map lookup ld/st (80)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa1a6a8a9acbranch mispredict (cb)cdcfd0d5d6ddinst fetch restart (de)e0? int output thing (e9)ld/st retires (ed)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
302041300389740130023119417254010010100200001000010020000100005006214979148010341130013130070130038125476191262463010020010000200002001000020000130093130042112020110099100101001000010001000000001131012162212952510000100001000010100130039130039130039130039130087
30204130038974013002311941725401001010020000100001182000010000500621497914801034113001313003813003812547931262493010020010000200002001000020000130079130055112020110099100101001000010001000000000131012162212952510000100001000010100130039130039130039130075130039
302041300389743013005311941725401001010020000100001002000010000500621497914801034113001313003813003812547731262463010020010000200002001000020000130070130082112020110099100101001000010001000000000131012162212952510000100001000010100130039130039130039130039130039
30204130038974013002311941725401001010020000100001002000010000500621497914801034013001313003813003812547631262463010020010063200002001000020000130074130038112020110099100101001000010001000000010131012162212952510000100001000010100130039130039130039130039130039
30204130038974013002311941725401001010020000100001002000010000500621497914801034113001313003813003812547631262463010020010000200002001000020000130081130050112020110099100101001000010001000000000131012162212952510000100001000010100130039130039130039130039130039
30204130038975013002311941725401001010020000100001002000010000500621497914801034113001313003813003812547631262463010020010000200002001000020000130085130039112020110099100101001000010001000000000131002162212952510000100001000010100130039130039130039130039130039
30204130038973013002311941725401001010020000100001002000010000500621497914801034113001313003813003812547631262463010020010000200002001000020000130104130046112020110099100101001000010001000000000131012162312952610000100001000010100130043130039130039130039130039
30204130038974013002311941725401001010020000100001002000010000500621497914801034013001313003813003812547631262463010020010000200002001000020000130103130058112020110099100101001000010001000000000131012162212952510000100001000010100130039130039130039130039130039
30204130038974013002311941725401001010020000100001002000010000500621497914801034113001313003813003812547631262463010020010000200002001000020000130091130051112020110099100101001000010001000000000131012162212952510000100001000010100130039130039130039130039130039
30204130038974013002311941725401001010020000100001002000010000500621497914801034113001313003813003812547631262463010020010000200002001000020000130075130041112020110099100101001000010001000000000131012162212960710000100001000010100130039130039130039130039130039

1000 unrolls and 10 iterations

Result (median cycles for code): 13.0038

retire (01)cycle (02)03080b18191e1f3f4f51inst issue (52)~issue int (53)~issue fp/simd (54)~issue ld/st (55)~dispatch int (56)~dispatch fp/simd (57)~dispatch ld/st (58)huge thing int (59)huge thing ld/st (5a)huge thing fp/simd (5b)60696b6d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op ld/st (7d)~map op fp/simd (7e)~map lookup int (7f)~map lookup ld/st (80)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa0a1a6a7a8a9acc5cfd5d6ddinst fetch restart (de)e0? int output thing (e9)ld/st retires (ed)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
300241300389740000001300231194172540010100102000010000102000010000506214979148000251130013013003813003812549831262743001020100002000020100002000013003813003811200211091010010100001000100000000012701171112952510000100001000010010130039130039130039130039130063
300241300389740000901300231194172540010100102000010000102000010000506214979148000250130013013003813003812549831262683001020100002000020100002000013003813003811200211091010010100001000100000000012701161112952810000100001000010010130039130039130039130039130039
300241300389740000001300231194172540012100122000010000102000010000506214979148000251130013013003813003812549831262683001020100002000020100002013113003813003811200211091010010100001000100000000012701161112952510002100001000010010130039130039130040130039130039
300241300389740000001300231194172540010100102000010000122000010000506214979148001390130013013003913007612549831262683001020100002000020100002000013003813003811200221091010010100001000100000000012701161112952510000100001000010010130039130039130039130039130039
300241300389740000001300231194172540010100102000010000102000010000506214979148000251130013013003813003812549831262683001020100002000020100002000013003813003811200211091010010100001002100000000012701161412953110007100001000010010130039130039130039130039130039
300241300389740100001300231194172540010100102000010000102000010000506214979148000251130013013003813003812549831262683001220100002000020100002000013003813003811200221091010010100001000100000000012701161112952510000100001000010010130044130045130039130039130046
300241300389740000001300231194142540012100102000010000102000010000506214979148000251130013013003813003812549831262683001020100002000020100002000013003813003811200211091010010100001000100000000012701161112952510000100001000010010130039130039130039130039130039
300241300389740000001300231194172540010100102000010000102000010000506214979148000250130013013003813003812549831262683001020100002000020100002000013003813003811200211091010010100001000100000000012701161112952510000100001000010010130039130039130039130039130039
300241300389740000001300231194172540010100102000010000102000010000506214979148000250130013013003813003812549831262683001020100002000020100002000013003813003811200211091010010100001000100000000012701161212952510000100001000010010130042130039130039130039130039
300241300389740000001300231194172540010100102000010000122000010000606214968148000480130013013003813003812549831262683001020100002000020100002000013003813003811200211091010010100001000100000000012701161112952510000100001000010010130039130039130039130039130039

Test 3: throughput

Count: 8

Code:

  fcvtps x0, d8
  fcvtps x1, d8
  fcvtps x2, d8
  fcvtps x3, d8
  fcvtps x4, d8
  fcvtps x5, d8
  fcvtps x6, d8
  fcvtps x7, d8
  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

retire (01)cycle (02)0307080b18191e1f3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)9fa0a1a6a8a9acc5branch mispredict (cb)cdcfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
16020440053310100001207425240104801001600041001600205001440132140022400414004119977619992160120200160032200160032400414004111802011009910080100100000000111511701600400388000080000801004004240042400424004240042
1602044004131000000003225240104801001600041001600205001440132140022400414004119977619992160120200160032200160032400414004111802011009910080100100000000111511701600400388000080000801004004240042400424004240042
1602044004131100000003225240104801001600041001600205001440132140022400414004119977619992160120200160032200160032400414004111802011009910080100100000000111511701600400388000080000801004004240042400424004240042
1602044004131000000003225240104801001600041001600205001440132040022400414004119977619992160120200160032200160032400414004111802011009910080100100000100111511701600400388000080000801004004240042400424004240042
16020440041310000000032120240104801001600041001600205001440132140022400414004119977619992160120200160032200160032400414004111802011009910080100100000100111511701600400388000080000801004004240042400424004240042
1602044004131000000003225240104801001600041001600205001440132140022400414004119977619992160120200160032200160032400414004111802011009910080100100000000111511701600400388000080000801004004240042400424004240042
16020440041310000000069725240104801001600041001600205001440132140022400414004119977619992160120200160032200160032400414004111802011009910080100100000000111511701600400388000080000801004004240042400424004240042
1602044004131000000003225240104801001600041001600205001440132140022400414004119977619992160120200160032200160032400414004111802011009910080100100000000111511701600400388000080000801004004240042400424004240042
1602044004132200000003225240104801001600041001600205001440132040022400414004119977619992160120200160032200160032400414004111802011009910080100100000000111511701600400388000080000801004004240042400424004240042
1602044004131100000007425240104801001600041001600205001440132040022400414004119977619992160120200160032200160032400414004111802011009910080100100000000111511701600400388000080000801004004240042400424004240042

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

retire (01)cycle (02)031e3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696b6d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)9fa8accfd5d6ddinst fetch restart (de)e0? int output thing (e9)ea? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
160024400543000422524001080010160000101600005014400000400220400414004119996320021160010201600002016000040041400411180021109108001010005020516324003880000080000800104004240042400424004240042
160024400413000422524001080010160000101600005014400001400220400414004119996320021160010201600002016000040041400411180021109108001010005020316334003880000080000800104004240042400424004240042
160024400413000422524001080010160000101600005014400000400220400414004119996320021160010201600002016000040041400411180021109108001010005020216234003880000080000800104004240042400424004240042
160024400412990632524001080010160000101600005014400000400220400414004119996320021160010201600002016000040041400411180021109108001010005020316324003880000080000800104004240042400424004240042
160024400413000424924030880010160000101600005014400001401500401214004119996320021160010201600002016000040041400411180021109108001010005020316234003880000080000800104004240042400424004240042
1600244004130012842524001080010160000101600005014400000400220400414004119996320021160010201600002016000040041400411180021109108001010005020316644003880000080000800104004240042400424004240042
1600244004130004225240010800101600001016000050144000014002204004140041199963200211600102016000020160000400414004111800211091080010101155020316334003880000080000800104004240042400424004240042
160024400412990422524001080010160000101600005014400000400220400414004119996320021160010201600002016000040041400411180021109108001010005020216234003880000080000800104004240042400424004240042
160024400413000422524001080010160000101600005014400000400220400414004119996320021160010201602202016000040041400411180021109108001010005020316334003880000080000800104004240042400424004240042
160024400413000422524001080010160000101600005014400000400220400414004119996320021160010201600002016000040041400411180021109108001010005020316324003880000080000800104004240042400424004240042