Apple M1 Microarchitecture Research by Dougall Johnson

Firestorm: Overview | Base Instructions | SIMD and FP Instructions
Icestorm:  Overview | Base Instructions | SIMD and FP Instructions

FCVTPS (scalar, H to W)

Test 1: uops

Code:

  fcvtps w0, h0
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 3.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 2.000

retire (01)cycle (02)031e3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch fp/simd (57)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op fp/simd (7e)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst integer (97)a8accfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
2004541404325300010002000200018000152254154124832742000200020005415411110011000007331622538100010001000542542542542542
2004541404325300010002000200018000152254154124832742000200020005415411110011000007321622538100010001000542542542542542
2004541404325300010002000200018000152254154124832742000200020005415411110011000007321622538100010001000542542542542542
2004541404325300010002000200018000152254154124832742000200020005415411110011000007321622538100010001000542542542542542
2004541404325300010002000200018000152254154124832742000200020005415411110011000137321622538100010001000542542542542542
2004541404325300010002000200018000152254154124832742000200020005415411110011000007321622538100010001000542542542542542
2004541404325300010002000200018000152254154124832742000200020005415411110011000007321622538100010001000542542542542542
20045414124325300010002000200018000152254154124832742000200020005415411110011000007321622538100010001000542542542542542
2004541404325300010002000200018000152254154124832742000200020005415411110011000007321622538100010001000542542542542542
2004541404325300010002000200018000152254154124832742000200020005415411110011000007321622538100010001000542542542542542

Test 2: Latency 1->2 roundtrip

Code:

  fcvtps w0, h0
  fmov d0, x0
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 13.0038

retire (01)cycle (02)030818191e1f3f4f51inst issue (52)~issue int (53)~issue fp/simd (54)~issue ld/st (55)~dispatch int (56)~dispatch fp/simd (57)~dispatch ld/st (58)huge thing int (59)huge thing ld/st (5a)huge thing fp/simd (5b)60696b6d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op ld/st (7d)~map op fp/simd (7e)~map lookup int (7f)~map lookup ld/st (80)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa6a8a9acc2branch mispredict (cb)cdcfd0d5d6ddinst fetch restart (de)e0? int output thing (e9)ld/st retires (ed)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
3020413003897400000130023119416254010010100200001000010020000100005006214979148012621130013013006913004112547631262463010020010000200002001000020000130038130038112020110099100101001000010010000000000131012162212952510000100001000010100130039130039130039130039130039
3020413003997400000130023119417254010010100200001000010020000100005006214979148010341130013013003813003812547631262463010020010000200002001000020000130038130038112020110099100101001000010010000000000131013162212952510000100001000010100130039130039130039130039130039
3020413016197500000130023119417254010010100200001000010020000100005006214979148010340130013013003813006812547631262463010020010000200002001000020000130038130038112020110099100101001000010010000000000131012162212952510000100001000010100130039130039130039130039130039
3020413003897400000130023119417254010010100200001000010220117100005006214979148010341130013013003813003812550431262493010020010000200002001000020000130038130038112020110099100101001000010010000000000131012162212952510000100001000010100130039130039130039130039130039
3020413003897400000130023119417254010010100200001000010020000100005006214979148010341130013013003813003812547631262463010020010000200002001000020000130038130038112020110099100101001000010010000000000131012162212952510000100001000010100130039130039130039130039130039
3020413003897400000130024119417254010010100200001000010020000100495006215075148010340130013013003813003812547631262463010020010000200002001000020000130038130038112020110099100101001000010010000000000131012162212952510000100001000010100130039130039130039130039130039
3020413003897400000130023119417254010010100200001000010020000100005006214979148010341130013013003813003812547631262463010020010000200002001000020000130038130039112020110099100101001000010010000000000131012162212952510000100001000010100130039130039130039130039130039
3020413003897400000130023119417254010010100200001000010020000100005006214979148010341130013013003813003812547631262463010020010000200002001000020000130038130038112020110099100101001000010010000000000131013162212952510000100001000010100130039130039130039130039130039
3020413003897400000130085119417254010010100200001000010020000100005006214979148010341130013013003813003812547631262463010020010000200002001000020000130038130038112020110099100101001000010010000000001131012162212952510000100001000010100130039130039130039130039130039
3020413003997400000130023119417254010010100200001000010020000100005006214979148010341130013013003813003812547631262463010020010000200002001000020132130038130038112020110099100101001000010010000000000131012162212952510000100001000010100130039130039130039130039130039

1000 unrolls and 10 iterations

Result (median cycles for code): 13.0038

retire (01)cycle (02)0308090b18191e3f4f51inst issue (52)~issue int (53)~issue fp/simd (54)~issue ld/st (55)~dispatch int (56)~dispatch fp/simd (57)~dispatch ld/st (58)huge thing int (59)huge thing ld/st (5a)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op ld/st (7d)~map op fp/simd (7e)~map lookup int (7f)~map lookup ld/st (80)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa0a1a6a8acc5cdcfd5d6ddinst fetch restart (de)e0? int output thing (e9)ld/st retires (ed)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
3002413003897400000013002311941725400101001020000100001020000100005062149791480002511300131300381300381254983126268300102010000200002010000200001300381301021120021109101001010000100010000000012702161112952510000100001000010010130039130039130039130039130039
3002413003897400000013002311941725400101001020000100001020000100005062149791480002511300131300381300381254983126268300102010000200002010000200001300381300381120021109101001010000100010000000012704161112952510000100001000010010130039130039130039130039130039
3002413003897400000013002311941725400101001020000100001020000100005062149791480002511300131300381300381254983126268300102010000200002010000200001300381300381120021109101001010000100010000000012701161212952510000100001000010010130039130039130039130039130039
3002413003897400000013002311941725400101001020000100001020000100005062149791480002511300131300381300381254983126268300102010000200002010000200001300381301191120021109101001010000100010000000012701161112952510000100001000010010130039130039130039130039130039
3002413003897400000013002311941725400101001020000100001020000100005062149791480002511300131300381300381254983126268300102010000200002010000200001300381300381120021109101001010000100010000000012701163112952510000100001000010010130039130039130039130039130039
3002413003897400000013002311941725400101001020000100001020000100005062149791480002511300131300381300381254983126268300102010000200002010000200001300381300381120021109101001010000100010000000012701161112952510000100001000010010130039130039130039130039130039
3002413003897400000013002311941725400101001020000100001020000100005062149791480002511300131300381300381254983126268300102010000200002010000200001300381300681120021109101001010000100010000000012701161112952510000100001000010010130039130039130039130039130039
3002413003897400000013002311941725400101001020000100001020000100005062149791480002511300131300381300381254983126268300102010000200002010000200001300381300381120021109101001010000100010000000112701161112952510000100001000010010130039130039130039130039130039
30024130038974000008413002311941725400101001020000100011020000100005062149791480002511300131300381300381254983126268300102010000200002010000200001300381300381120021109101001010000100010000000012701161112952510000100001000010010130039130039130039130039130039
3002413003897300000013005311941725400101001020000100001020113100005062241271480002511300131300381300381254983126268300102010000200002010000200001300381300381120021109101001010000100010000000012701161112952510000100001000010010130039130039130039130039130039

Test 3: throughput

Count: 8

Code:

  fcvtps w0, h8
  fcvtps w1, h8
  fcvtps w2, h8
  fcvtps w3, h8
  fcvtps w4, h8
  fcvtps w5, h8
  fcvtps w6, h8
  fcvtps w7, h8
  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5006

retire (01)cycle (02)030b18191e3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)9fa6acc2c5branch mispredict (cb)cdcfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
1602044004131000003225240104801001600041001600205001440132140022400414004119972619992160120200160032200160032400414004111802011009910080100100000111511701600400388000080000801004004240042400424004240042
1602044004131000003225240104801001600041001600205001440132040022400414004119977619992160120200160032200160032400414004111802011009910080100100000111511701600400388000080000801004004240042400424004240042
1602044004131000003225240104801001600041001600205001440132140022400414004119977619992160120200160032200160032400414004111802011009910080100100000111511701600400388000080000801004004240042400424004240042
1602044004131000003225240104801001600041001600205001440132040022400414004119977619992160120200160032200160032400414004111802011009910080100100000222512712411400488000480000801004005240052400524005340053
1602044005131000006627240116801041600121001600285001440202040032400514005119976919989160128200160038200160038400514005211802011009910080100100000222512812411400488000480000801004005340053400524005240052
16020440051310000012226240116801041600121001600285001440202140032400524005219976919989160128200160038200160038400514005211802011009910080100100000222512812411400488000480000801004005240052400534005340053
1602044005231000006627240116801041600121001600285001440202140032400514005119976919989160128200160038200160038400524005111802011009910080100100000222512712411400488000480000801004005340052400524005240052
1602044005231000006627240116801041600121001600285001440202140032400514005219976919989160128200160038200160038400524005211802011009910080100100000222512812411400498000480000801004005340053400524005240052
16020440052310000066272401168010416001210016002850014402021400324005140051199761019989160128200160038200160038400514005111802011009910080100100000222512712411400498000480000801004005240052400524005240052
1602044005131000006626240116801041600121001600285001440202140032400524005119976919989160128200160038200160038400524005111802011009910080100100000222512712411400498000480000801004005340053400534005340053

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

retire (01)cycle (02)030b1e1f3a3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)91inst b.cc (94)inst integer (97)9fa8accfd0d2d5d6d9dadbddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
1600244005531000004225240010800101600001016000050144000004002240041400411999632002116001020160000201600004004140041118002110901080010100050200091600588400388000080000800104004240042400424004240042
160024400413110000422524001080010160000101600005014400000400224004140041199963200211600102016000020160000400414004111800211090108001010005020009160031110400388000080000800104004240042400424004240042
1600244004131000009825240010800101600001016000050144000004002240041400411999632002116001020160000201600004004140041118002110901080010100050200091600499402278000080000800104004240042400424004240042
16002440041310100042252400108001016000010160000501440000140022400414004119996320021160010201600002016000040041400411180021109010800101019502000416003811400388000080000800104004240042400424004240042
16002440041310000042252400108001016000010160000501440000140022400414004119996320021160010201600002016000040041400411180021109010800101000502000916004128400388000080000800104004240042400424004240042
16002440041311000042252400108001016000010160000501440000140022400414004119996320021160010201600002016000040041400411180021109010800101000502000916003124400388000080000800104004240042400424004240042
1600244004131000004225240010800101600001016000050144000004002240041400411999632002116001020160000201600004004140041118002110901080010100050200091600449400388000080000800104004240042400424004240042
160024400413110000422524001080010160000101600005014400000400224004140041199963200211600102016000020160000400414004111800211090108001010005020009160031316400388000080000800104004240042400424004240042
16002440041321000042252400108001016000010160000501440000140022400414004119996320021160010201600002016000040041400411180021109010800101000502000516003104400388000080000800104004240042400424004240042
1600244004131100007025240010800101600001016000050144000004002240041400411999632002116001020160000201600004004140041118002110901080010100050200051600383400388000080000800104004240042400424004240042