Firestorm: FCVTPS (scalar, H to X) measurements

Code:

  fcvtps x0, h0

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 3.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 2.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
2004	541	4	0	0	43	25	3000	1000	2000	2000	18000	1	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	73	1	16	1	1	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	0	43	25	3000	1000	2000	2000	18000	1	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	73	1	16	1	1	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	0	43	25	3000	1000	2000	2000	18000	0	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	73	1	16	1	1	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	9	43	25	3000	1000	2000	2000	18000	1	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	73	1	16	1	1	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	0	43	25	3000	1000	2000	2000	18000	0	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	73	1	16	2	2	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	0	43	25	3000	1000	2000	2000	18000	1	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	73	1	16	1	1	538	1000	1000	1000	542	542	542	542	542
2004	541	5	1	0	43	25	3000	1000	2000	2000	18000	0	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	73	1	16	1	1	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	0	43	25	3000	1000	2000	2000	18000	0	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	73	1	16	1	1	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	0	43	25	3000	1000	2000	2000	18000	0	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	73	1	16	1	1	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	0	43	25	3000	1000	2000	2000	18000	1	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	73	1	16	1	2	538	1000	1000	1000	542	542	542	542	542

Test 2: Latency 1->2 roundtrip

Code:

  fcvtps x0, h0
  fmov d0, x0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 13.0038

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	l2 tlb miss data (0b)	18	19	1e	3a	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30204	130038	974	1	0	0	0	0	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	0	130013	130038	130038	125476	3	126246	30100	200	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	1310	1	2	16	2	2	129551	10000	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	974	0	0	0	0	0	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	0	130013	130038	130038	125476	3	126246	30100	200	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	1310	1	2	16	2	2	129556	10000	10000	10000	10100	130043	130039	130039	130039	130044
30204	130040	974	0	0	0	0	0	0	130024	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	0	130013	130038	130038	125476	3	126246	30100	200	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	0	10004	0	0	0	0	1310	1	2	16	2	2	129559	10000	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	974	0	0	0	0	0	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	0	130013	130038	130038	125476	3	126246	30100	200	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	1310	1	2	16	2	2	129602	10000	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	974	0	0	0	0	0	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	0	130013	130038	130038	125476	3	126246	30100	200	10000	20128	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	2	0	0	0	1310	1	2	16	2	2	129578	10000	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	974	0	0	0	0	0	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	520	6217235	14801145	0	130013	130074	130093	125477	3	126246	30100	200	10000	20000	200	10061	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	1310	1	2	16	3	2	129525	10000	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	974	0	0	0	0	0	0	130023	119414	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	0	130013	130038	130074	125476	3	126246	30100	200	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	1310	1	2	16	5	2	129525	10000	10000	10000	10100	130041	130040	130113	130039	130039
30204	130038	974	0	0	0	0	0	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	0	130013	130038	130038	125476	3	126246	30100	200	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	1310	1	2	16	3	2	129525	10000	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	974	0	0	0	0	0	0	130026	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	0	130013	130038	130041	125476	3	126246	30100	200	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	2	0	3	0	1310	1	2	16	2	2	129525	10000	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	974	0	0	0	0	0	0	130023	119420	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	0	130013	130038	130038	125476	3	126277	30100	200	10000	20000	200	10000	20000	130113	130072	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	1310	1	2	17	2	2	129525	10000	10000	10000	10100	130039	130039	130039	130039	130039

1000 unrolls and 10 iterations

Result (median cycles for code): 13.0038

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk instruction (07)	l2 tlb miss data (0b)	0e	18	19	1e	1f	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30024	130038	1008	0	0	0	0	0	0	0	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	0	130013	130038	130038	125498	3	126268	30181	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	0	1270	1	16	1	1	129525	10000	10000	10000	10010	130039	130039	130039	130039	130039
30024	130038	1008	0	0	0	0	0	0	0	130024	119417	25	40010	10010	20000	10000	10	20000	10000	50	6215443	14800025	0	130013	130038	130038	125498	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	0	1270	1	16	1	1	129525	10000	10000	10000	10010	130039	130039	130039	130039	130039
30024	130038	1008	0	0	0	0	0	0	0	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	1	130013	130038	130038	125498	3	126268	30010	20	10000	20000	20	10000	20000	130039	130038	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	0	1270	1	16	1	1	129525	10000	10000	10000	10010	130039	130039	130039	130039	130039
30024	130038	1008	0	0	0	0	0	0	0	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	1	130013	130038	130038	125498	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	0	1270	1	16	1	1	129525	10000	10000	10000	10010	130121	130122	130295	130041	130167
30024	130205	1010	0	0	0	0	0	0	0	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	0	130013	130038	130038	125499	3	126270	30010	20	10000	20000	20	10000	20000	130039	130038	1	1	20021	10	9	10	10010	10000	10	0	0	10000	1	0	0	4	0	1325	2	24	1	2	129525	10000	10000	10000	10010	130039	130039	130039	130042	130039
30024	130038	1008	0	0	0	0	0	12	0	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800139	0	130013	130038	130038	125498	6	126270	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	60	0	0	1270	1	16	1	1	129525	10000	10000	10000	10010	130039	130039	130039	130039	130039
30024	130038	1008	0	0	0	0	0	0	0	130023	119417	25	40010	10012	20000	10000	10	20000	10000	50	6214979	14800025	0	130013	130038	130038	125498	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	0	1270	1	16	1	1	129525	10000	10000	10000	10010	130039	130039	130039	130039	130039
30024	130038	1008	0	0	0	0	0	0	0	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	0	130013	130038	130038	125498	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	0	1270	1	16	2	1	129525	10000	10000	10000	10010	130039	130039	130039	130039	130039
30024	130038	974	0	0	0	0	0	0	0	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	0	130013	130038	130038	125498	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	0	1270	1	16	1	1	129525	10000	10000	10000	10010	130039	130039	130039	130039	130039
30024	130038	974	1	0	0	0	0	0	0	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	1	130013	130038	130038	125498	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	1	1270	1	16	1	1	129525	10000	10000	10000	10010	130041	130039	130039	130039	130039

Test 3: throughput

Count: 8

Code:

  fcvtps x0, h8
  fcvtps x1, h8
  fcvtps x2, h8
  fcvtps x3, h8
  fcvtps x4, h8
  fcvtps x5, h8
  fcvtps x6, h8
  fcvtps x7, h8

Initialization

  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	19	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	40062	300	0	0	118	25	240104	80100	160004	100	160020	500	1440132	1	40022	40041	40041	19977	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	0	1	1	1	5117	4	16	0	40038	80000	80000	80100	40042	40042	40042	40042	40042
160204	40041	299	0	0	32	49	240104	80100	160004	100	160020	500	1440132	1	40022	40041	40041	19977	6	20037	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	0	1	1	1	5117	0	16	0	40038	80000	80000	80100	40042	40042	40042	40042	40042
160204	40041	300	0	0	32	25	240104	80100	160004	100	160020	500	1440132	1	40022	40041	40041	19977	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	0	1	1	1	5117	0	16	0	40038	80000	80000	80100	40042	40042	40042	40042	40042
160204	40041	300	0	0	32	25	240104	80100	160004	100	160020	500	1440132	1	40022	40041	40041	19977	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	0	1	1	1	5117	0	16	0	40038	80000	80000	80100	40042	40042	40042	40042	40042
160204	40041	300	0	0	32	25	240104	80100	160004	100	160020	500	1440132	1	40022	40041	40041	19977	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	0	1	1	1	5117	0	16	0	40038	80000	80000	80100	40042	40042	40042	40042	40042
160204	40041	300	0	0	32	25	240104	80100	160004	100	160020	500	1440132	1	40022	40041	40041	19977	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	0	1	1	1	5117	0	16	0	40038	80000	80000	80100	40042	40042	40042	40042	40042
160204	40041	300	0	0	283	25	240104	80100	160004	100	160020	500	1440132	0	40022	40041	40041	19977	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	0	1	1	1	5117	0	16	0	40038	80000	80000	80100	40042	40042	40042	40042	40042
160204	40041	299	0	0	32	25	240104	80100	160004	100	160020	500	1440132	0	40022	40041	40041	19977	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	0	1	1	1	5117	0	16	0	40038	80000	80000	80100	40042	40042	40042	40042	40042
160204	40041	300	0	0	32	25	240104	80100	160004	100	160020	500	1440132	0	40022	40041	40041	19977	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	0	1	1	1	5117	0	16	0	40038	80087	80000	80100	40042	40042	40042	40042	40042
160204	40041	300	0	0	32	25	240104	80100	160004	100	160020	500	1440132	0	40022	40041	40041	19977	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	2	0	0	1	1	1	5117	0	16	0	40038	80000	80000	80100	40042	40042	40042	40042	40042

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	ac	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	40054	300	0	707	25	240010	80010	160000	10	160000	50	1440000	1	40022	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	5020	18	16	7	5	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	300	0	42	25	240010	80010	160000	10	160000	50	1440000	1	40022	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	5020	8	16	9	7	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	300	0	392	58	240010	80010	160000	10	160000	50	1440000	1	40022	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	5020	5	16	10	9	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	300	0	42	25	240010	80010	160000	10	160000	50	1440000	1	40022	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	5020	5	16	10	9	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	299	0	42	25	240010	80010	160000	10	160000	50	1440000	1	40022	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	5020	8	16	10	7	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	300	0	42	25	240010	80010	160000	10	160000	50	1440000	0	40022	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	5020	8	16	5	8	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	300	0	42	25	240010	80010	160000	10	160000	50	1440000	0	40022	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	5020	8	16	8	10	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	300	0	42	25	240010	80010	160000	10	160000	50	1440000	0	40022	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	5020	4	16	8	6	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	300	0	42	25	240010	80010	160000	10	160000	50	1440000	1	40022	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	5020	7	16	10	7	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	300	0	707	25	240010	80010	160000	10	160000	50	1440000	1	40022	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	5020	6	16	5	8	40038	80000	80000	80010	40042	40042	40042	40042	40042

FCVTPS (scalar, H to X)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations