Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FCVTPS (scalar, H to X)

Test 1: uops

Code:

  fcvtps x0, h0
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 3.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 2.000

retire uop (01)cycle (02)03mmu table walk instruction (07)1e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst int alu (97)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
20045414004325300010002000200018000152254154124832742000200020005415411110011000007311611538100010001000542542542542542
20045414004325300010002000200018000152254154124832742000200020005415411110011000007311611538100010001000542542542542542
20045414004325300010002000200018000052254154124832742000200020005415411110011000007311611538100010001000542542542542542
20045414094325300010002000200018000152254154124832742000200020005415411110011000007311611538100010001000542542542542542
20045414004325300010002000200018000052254154124832742000200020005415411110011000007311622538100010001000542542542542542
20045414004325300010002000200018000152254154124832742000200020005415411110011000007311611538100010001000542542542542542
20045415104325300010002000200018000052254154124832742000200020005415411110011000007311611538100010001000542542542542542
20045414004325300010002000200018000052254154124832742000200020005415411110011000007311611538100010001000542542542542542
20045414004325300010002000200018000052254154124832742000200020005415411110011000007311611538100010001000542542542542542
20045414004325300010002000200018000152254154124832742000200020005415411110011000007311612538100010001000542542542542542

Test 2: Latency 1->2 roundtrip

Code:

  fcvtps x0, h0
  fmov d0, x0
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 13.0038

retire uop (01)cycle (02)03l1i tlb fill (04)l2 tlb miss data (0b)18191e3a3f4f51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
3020413003897410000013002311941725401001010020000100001002000010000500621497914801034013001313003813003812547631262463010020010000200002001000020000130038130038112020110099100101001000010000100000000131012162212955110000100001000010100130039130039130039130039130039
3020413003897400000013002311941725401001010020000100001002000010000500621497914801034013001313003813003812547631262463010020010000200002001000020000130038130038112020110099100101001000010000100000000131012162212955610000100001000010100130043130039130039130039130044
3020413004097400000013002411941725401001010020000100001002000010000500621497914801034013001313003813003812547631262463010020010000200002001000020000130038130038112020110099100101001000010000100040000131012162212955910000100001000010100130039130039130039130039130039
3020413003897400000013002311941725401001010020000100001002000010000500621497914801034013001313003813003812547631262463010020010000200002001000020000130038130038112020110099100101001000010000100000000131012162212960210000100001000010100130039130039130039130039130039
3020413003897400000013002311941725401001010020000100001002000010000500621497914801034013001313003813003812547631262463010020010000201282001000020000130038130038112020110099100101001000010000100002000131012162212957810000100001000010100130039130039130039130039130039
3020413003897400000013002311941725401001010020000100001002000010000520621723514801145013001313007413009312547731262463010020010000200002001006120000130038130038112020110099100101001000010000100000000131012163212952510000100001000010100130039130039130039130039130039
3020413003897400000013002311941425401001010020000100001002000010000500621497914801034013001313003813007412547631262463010020010000200002001000020000130038130038112020110099100101001000010000100000000131012165212952510000100001000010100130041130040130113130039130039
3020413003897400000013002311941725401001010020000100001002000010000500621497914801034013001313003813003812547631262463010020010000200002001000020000130038130038112020110099100101001000010000100000000131012163212952510000100001000010100130039130039130039130039130039
3020413003897400000013002611941725401001010020000100001002000010000500621497914801034013001313003813004112547631262463010020010000200002001000020000130038130038112020110099100101001000010000100002030131012162212952510000100001000010100130039130039130039130039130039
3020413003897400000013002311942025401001010020000100001002000010000500621497914801034013001313003813003812547631262773010020010000200002001000020000130113130072112020110099100101001000010000100000000131012172212952510000100001000010100130039130039130039130039130039

1000 unrolls and 10 iterations

Result (median cycles for code): 13.0038

retire uop (01)cycle (02)03mmu table walk instruction (07)l2 tlb miss data (0b)0e18191e1f3f4f51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
3002413003810080000000130023119417254001010010200001000010200001000050621497914800025013001313003813003812549831262683018120100002000020100002000013003813003811200211091010010100001000100000000012701161112952510000100001000010010130039130039130039130039130039
3002413003810080000000130024119417254001010010200001000010200001000050621544314800025013001313003813003812549831262683001020100002000020100002000013003813003811200211091010010100001000100000000012701161112952510000100001000010010130039130039130039130039130039
3002413003810080000000130023119417254001010010200001000010200001000050621497914800025113001313003813003812549831262683001020100002000020100002000013003913003811200211091010010100001000100000000012701161112952510000100001000010010130039130039130039130039130039
3002413003810080000000130023119417254001010010200001000010200001000050621497914800025113001313003813003812549831262683001020100002000020100002000013003813003811200211091010010100001000100000000012701161112952510000100001000010010130121130122130295130041130167
3002413020510100000000130023119417254001010010200001000010200001000050621497914800025013001313003813003812549931262703001020100002000020100002000013003913003811200211091010010100001000100001004013252241212952510000100001000010010130039130039130039130042130039
300241300381008000001201300231194172540010100102000010000102000010000506214979148001390130013130038130038125498612627030010201000020000201000020000130038130038112002110910100101000010001000000600012701161112952510000100001000010010130039130039130039130039130039
3002413003810080000000130023119417254001010012200001000010200001000050621497914800025013001313003813003812549831262683001020100002000020100002000013003813003811200211091010010100001000100000000012701161112952510000100001000010010130039130039130039130039130039
3002413003810080000000130023119417254001010010200001000010200001000050621497914800025013001313003813003812549831262683001020100002000020100002000013003813003811200211091010010100001000100000000012701162112952510000100001000010010130039130039130039130039130039
300241300389740000000130023119417254001010010200001000010200001000050621497914800025013001313003813003812549831262683001020100002000020100002000013003813003811200211091010010100001000100000000012701161112952510000100001000010010130039130039130039130039130039
300241300389741000000130023119417254001010010200001000010200001000050621497914800025113001313003813003812549831262683001020100002000020100002000013003813003811200211091010010100001000100000000112701161112952510000100001000010010130041130039130039130039130039

Test 3: throughput

Count: 8

Code:

  fcvtps x0, h8
  fcvtps x1, h8
  fcvtps x2, h8
  fcvtps x3, h8
  fcvtps x4, h8
  fcvtps x5, h8
  fcvtps x6, h8
  fcvtps x7, h8
  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

retire uop (01)cycle (02)03191e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)fetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
16020440062300001182524010480100160004100160020500144013214002240041400411997761999216012020016003220016003240041400411180201100991008010010000011151174160400388000080000801004004240042400424004240042
1602044004129900324924010480100160004100160020500144013214002240041400411997762003716012020016003220016003240041400411180201100991008010010000011151170160400388000080000801004004240042400424004240042
1602044004130000322524010480100160004100160020500144013214002240041400411997761999216012020016003220016003240041400411180201100991008010010000011151170160400388000080000801004004240042400424004240042
1602044004130000322524010480100160004100160020500144013214002240041400411997761999216012020016003220016003240041400411180201100991008010010000011151170160400388000080000801004004240042400424004240042
1602044004130000322524010480100160004100160020500144013214002240041400411997761999216012020016003220016003240041400411180201100991008010010000011151170160400388000080000801004004240042400424004240042
1602044004130000322524010480100160004100160020500144013214002240041400411997761999216012020016003220016003240041400411180201100991008010010000011151170160400388000080000801004004240042400424004240042
16020440041300002832524010480100160004100160020500144013204002240041400411997761999216012020016003220016003240041400411180201100991008010010000011151170160400388000080000801004004240042400424004240042
1602044004129900322524010480100160004100160020500144013204002240041400411997761999216012020016003220016003240041400411180201100991008010010000011151170160400388000080000801004004240042400424004240042
1602044004130000322524010480100160004100160020500144013204002240041400411997761999216012020016003220016003240041400411180201100991008010010000011151170160400388008780000801004004240042400424004240042
1602044004130000322524010480100160004100160020500144013204002240041400411997761999216012020016003220016003240041400411180201100991008010010020011151170160400388000080000801004004240042400424004240042

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9faccdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
160024400543000707252400108001016000010160000501440000140022400414004119996320021160010201600002016000040041400411180021109108001010005020181675400388000080000800104004240042400424004240042
1600244004130004225240010800101600001016000050144000014002240041400411999632002116001020160000201600004004140041118002110910800101000502081697400388000080000800104004240042400424004240042
160024400413000392582400108001016000010160000501440000140022400414004119996320021160010201600002016000040041400411180021109108001010005020516109400388000080000800104004240042400424004240042
16002440041300042252400108001016000010160000501440000140022400414004119996320021160010201600002016000040041400411180021109108001010005020516109400388000080000800104004240042400424004240042
16002440041299042252400108001016000010160000501440000140022400414004119996320021160010201600002016000040041400411180021109108001010005020816107400388000080000800104004240042400424004240042
1600244004130004225240010800101600001016000050144000004002240041400411999632002116001020160000201600004004140041118002110910800101000502081658400388000080000800104004240042400424004240042
16002440041300042252400108001016000010160000501440000040022400414004119996320021160010201600002016000040041400411180021109108001010005020816810400388000080000800104004240042400424004240042
1600244004130004225240010800101600001016000050144000004002240041400411999632002116001020160000201600004004140041118002110910800101000502041686400388000080000800104004240042400424004240042
16002440041300042252400108001016000010160000501440000140022400414004119996320021160010201600002016000040041400411180021109108001010005020716107400388000080000800104004240042400424004240042
16002440041300070725240010800101600001016000050144000014002240041400411999632002116001020160000201600004004140041118002110910800101000502061658400388000080000800104004240042400424004240042