Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FCVTPS (scalar, S to S)

Test 1: uops

Code:

  fcvtps s0, s0
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100430372306125472510001000100039816013018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
1004303723010325472510001000100039816013018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
100430372308225472510001000100039816013018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
100430372306125472510001000100039816013018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
100430372408425472510001000100039816013018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
100430372306125472510001000100039816013018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
1004303724013425472510001000100039816013018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
100430372406125472510001000100039816013018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
100430372306125472510001000100039816003018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
100430372306125472510001000100039816013018303730372414328951000100010003037303711100110004673116112629100030383038303830383038

Test 2: Latency 1->2

Code:

  fcvtps s0, s0
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)1e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0ec? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204300372330000612954725101001001000010010000500427716013001830037300372826432874510100200100002001000030037300371110201100991001001000010018071021611296330100001003003830038300383003830038
1020430037233000061295472510100100100001001000050042771601300183003730037282643287451010020010000200100003003730037111020110099100100100001000071011611296330100001003003830038300383003830038
1020430037233000061295472510100100100001001000050042771601300183003730037282643287451010020010000200100003003730037111020110099100100100001000071011611296330100001003003830038300383003830038
1020430037233000061295472510100100100001001000050042771600300183003730037282673287451010020010000200100003003730037111020110099100100100001000071011611296330100001003003830038300383003830038
1020430037233000061295472510100100100001001000050042771600300183003730037282643287451010020010000200100003003730037111020110099100100100001000071011611296330100001003003830038300383003830038
1020430037233000061295472510100100100001001000050042771600300183003730037282643287451010020010000200100003003730037111020110099100100100001000071011611296330100001003003830038300383003830038
1020430037232000061295472510100100100001001000050042771600300183003730037282643287451010020010000200100003003730037111020110099100100100001000071011611296330100001003003830038300383003830038
10204300372330000131295472510100100100001001000050042771600300183003730037282643287451010020010000200100003003730037111020110099100100100001000071011611296330100001003003830038300383003830038
10204300372320000251295472510100100100001001000050042771600300183003730037282643287451010020010000200100003003730037111020110099100100100001000071011611296330100001003003830038300383003830038
1020430037233000061295472510100100100001001000050042771600300183003730037282643287451010020010000200100003003730037111020110099100100100001000071011611296330100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1002430037225000000612954725100101010000101000050427716013001830037300372828632876710010201000020100003003730037111002110910101000010000000006403162229629010000103003830038300383003830038
1002430037225000000612954725100101010000101000050427716003001830037300372828632876710010201000020100003003730037111002110910101000010000000006402162229629010000103003830038300383003830038
1002430037225000000612954725100101010000101000050427716003001830037300372828632876710010201000020100003003730037111002110910101000010000000006402162229629010000103003830038300383003830038
1002430037225000000612954725100101010000101000050427716003001830037300372828632876710010201000020100003003730037111002110910101000010000000006402162229629010000103003830038300383003830038
1002430037224000000612954725100101010000101000050427716013001830037300372828632876710010201000020100003003730037111002110910101000010000000006402162229629010000103003830038300383003830038
1002430037224000000612954725100101010000101000050427716013001830037300372828632876710010201000020100003003730037111002110910101000010000000006402162229629010000103003830038300383003830038
1002430037225000000612954725100101010000101000050427716013001830037300372828632876710010201000020100003003730037111002110910101000010000000006402162229629010000103003830038300383003830038
1002430037225000000612954725100101010000101000050427716013001830037300372828632876710010201000020100003003730037111002110910101000010000000006402162229629010000103003830038300383003830038
1002430037225000000612954725100101010000101000050427716013001830037300372828632876710010201000020100003003730037111002110910101000010000000006402162229629010000103003830038300383003830038
1002430037225000000612954725100101010000101000050427716013001830037300372828632876710010201000020100003003730037111002110910101000010000000006402162229629010000103003830038300383003830038

Test 3: throughput

Count: 8

Code:

  fcvtps s0, s8
  fcvtps s1, s8
  fcvtps s2, s8
  fcvtps s3, s8
  fcvtps s4, s8
  fcvtps s5, s8
  fcvtps s6, s8
  fcvtps s7, s8
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
80204200591560000003025801081008000810080020500640132020020200392003999770699908012020080032200800322003920039118020110099100100800001000000000111511811600200360800001002004020040200402004020040
80204200391560000003025801081008000810080020500640132020020200392003999770699908012020080032200800322003920039118020110099100100800001000000000111511801600200360800001002004020040200402004020040
80204200391550000003025801081008000810080020500640132020020200392003999770699908012020080032200800322003920039118020110099100100800001000002000111511801600200360800001002004020040200402004020040
80204200391560000603025801081008000810080020500640132020020200392003999770699908012020080032200800322003920039118020110099100100800001000001000111511801600200360800001002004020040200402004020040
80204200391560000003025801081008000810080020500640132020020200392003999890699908012020080032200800322003920039118020110099100100800001000000000111511801600200360800001002004020040200402004020040
80204200391550000003025801081008000810080020500640132020020200392003999770699908012020080032200800322003920039118020110099100100800001000002000111511801600200360800001002004020040200402004020040
802042003915500001205225801081008000810080020500640132020020200392003999770699908012020080032200800322003920039118020110099100100800001000000000111511801600200360800001002004020040200402004020040
80204200391550000003025801081008000810080020500640132020020200392003999770699908012020080032200800322003920039118020110099100100800001000000000111511801600200360800001002004020040200402004020040
80204200391550000003025801081008000810080020500640132020020200392003999770699908012020080032200800322003920039118020110099100100800001000000000111511801600200360800001002004020040200402004020040
80204200391550000003025801081008000810080020500640132020020200392003999770699908012020080032200800322003920039118020110099100100800001000000000111511801600200360800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03l1i tlb fill (04)mmu table walk data (08)1e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accdcfd2d5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
800242005015520082258001010800001080000506400000200200200392003999963100198001020800002080000200392003911800211091010800001000050200116112003680000102004020040200402004020040
800242003915500040258001010800001080000506400000200200200392003999963100198001020800002080000200392003911800211091010800001000050200116112003680000102004020040200402004020040
800242003915500040258001010800001080000506400000200200200392003999963100198001020800002080000200392003911800211091010800001000050200116112003680000102004020040200402004020040
8002420039155001261258001010800001080000506400000200200200392003999963100198001020800002080000200392003911800211091010800001000050200116112003680000102004020040200402004020040
800242003915500040258001010800001080000506400000200200200392003999963100198001020800002080000200392003911800211091010800001000050200116112003680000102004020040200402004020040
800242003915600040258001010800001080000506400000200200200392003999963100198001020800002080000200392003911800211091010800001000050200116112003680000102004020040200402004020040
800242003915600040258001010800001080000506400000200200200392003999963100198001020800002080000200392003911800211091010800001000050200116112003680000102004020040200402004020040
800242003915500040258001010800001080000506400000200200200392003999963100198001020800002080000200392003911800211091010800001000050200116112003680000102004020040200402004020040
800242003915500040258001010800001080000506400000200200200392003999963100198001020800002080000200392003911800211091010800001000050200116112003680000102004020040200402004020040
800242003915500040258001010800001080000506400000200200200392003999963100198001020800002080000200392003911800211091010800001000050200116112003680000102004020040200402004020040