Apple M1 Microarchitecture Research by Dougall Johnson

Firestorm: Overview | Base Instructions | SIMD and FP Instructions
Icestorm:  Overview | Base Instructions | SIMD and FP Instructions

FCVTPS (scalar, S to W)

Test 1: uops

Code:

  fcvtps w0, s0
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 3.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 2.000

retire (01)cycle (02)031e3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch fp/simd (57)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op fp/simd (7e)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst integer (97)a8accfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
2004541404325300010002000200018000152254154124832742000200020005415411110011000007311611538100010001000542542542542542
2004541404325300010002000200018000152254154124832742000200020005415411110011000107311611538100010001000542542542542542
2004541404325300010002000200018000152254154124832742000200020005415411110011000007311611538100010001000542542542542542
2004541404325300010002000200018000152254154124832742000200020005415411110011000007311611538100010001000542542542542542
2004541504325300010002000200018000152254154124832742000200020005415411110011000007311611538100010001000542542542542542
2004541404325300010002000200018000152254154124832742000200020005415411110011000007311611538100010001000542542542542542
2004541404325300010002000200018000152254154124832742000200020005415411110011000007311611538100010001000542542542542542
2004541408525300010002000200018000152254154124832742000200020005415411110011000207311611538100010001000542542542542542
2004541406425300010002000200018000152254154124832742000200020005415411110011000007311611538100010001000542542542542542
2004541408525300010002000200018000152254154124832742000200020005415411110011000007311622538100010001000542542542542542

Test 2: Latency 1->2 roundtrip

Code:

  fcvtps w0, s0
  fmov d0, x0
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 13.0038

retire (01)cycle (02)030818191e1f3a3f4f51inst issue (52)~issue int (53)~issue fp/simd (54)~issue ld/st (55)~dispatch int (56)~dispatch fp/simd (57)~dispatch ld/st (58)huge thing int (59)huge thing ld/st (5a)huge thing fp/simd (5b)60696b6d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op ld/st (7d)~map op fp/simd (7e)~map lookup int (7f)~map lookup ld/st (80)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa1a6a7a8a9acc5cdcfd0d5d6ddinst fetch restart (de)e0? int output thing (e9)ld/st retires (ed)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
302041300389740000001300231194182540100101002000010000100200001000050062149791480126201300130130038130038125476312624630100200100002000020010000200001300381300381120201100991001010010000100010000010000131012252212952510004100001000010100130213130039130039130039130039
3020413003897400012001300231194172540100101002000010000100200001000050062149791480103401300130130038130038125476312624730100200100002000020010000200001300401300381120201100991001010010000100010000010000131012162212952510000100001000010100130039130039130042130039130039
302041300389740000001300231194174640100101002000010000100200001000050062149791480103401300130130038130038125476312624630100200100002000020010000200001300381300381120201100991001010010000100010000010000131012162212952510000100001000010100130039130039130039130039130039
302041300389740000001300231194172540100101002000410000100200001000050062151711480103401300170130038130039125476312624630100200100002000020010000200001300381300381120201100991001010010000100010000000000131012162212952510000100001000010100130039130039130039130039130039
302041300389740000001300231194172540100101002000010000100200001000050062149791480103401300130130038130038125476312624630100200100002000020010000200001300381300381120201100991001010010000100010000000000131012163212952510000100001000010100130039130039130039130039130039
302041300389740000001300231194172540100101002000010000100200001000051162149791480103401300130130038130038125476312624630100200100002000020010000200001300381300381120201100991001010010000100010000000000131012162312952510000100001000010100130039130039130039130039130039
302041300389740000001300231194172540100101002000010000100200001000050062149791480103401300130130038130038125476312624630100200100002000020010000200001300401300391120201100991001010010000100010000010000131012162212952710000100001000010100130039130042130039130041130040
3020413003897400012001300231194172540100101002000010000100200001000050062149791480125801300130130117130043125476312624630100200100002000020010000200001300381300381120201100991001010010000100010000000000131012162112958910000100001000010100130041130039130039130039130039
302041300389740000001300231194172540100101002000010000100200001000050062149791480103401300130130038130038125476312624630100200100002000020010000200001300381300381120201100991001010010000100010000000000131012162212952510000100001000010100130039130039130039130039130039
302041300389740000001300231194172540100101002000010000100200001000050062149791480103401300130130038130038125476312624630100200100002000020010000200001300381300381120201100991001010010000100010000000000131012162212952510000100001000010100130039130039130039130039130039

1000 unrolls and 10 iterations

Result (median cycles for code): 13.0038

retire (01)cycle (02)0318191e3f4f51inst issue (52)~issue int (53)~issue fp/simd (54)~issue ld/st (55)~dispatch int (56)~dispatch fp/simd (57)~dispatch ld/st (58)huge thing int (59)huge thing ld/st (5a)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op ld/st (7d)~map op fp/simd (7e)~map lookup int (7f)~map lookup ld/st (80)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa0a1a6a8acc2c5cfd5d6ddinst fetch restart (de)e0? int output thing (e9)ld/st retires (ed)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
3002413003897400013002311941725400101001020000100001020000100005062149791480002501300131300901300621254993126268300102010000200002010000200001300381300381120022109101001010000100010000000012702163212957610000100001000010010130039130039130039130039130039
3002413003897300013002311941725400101001020000100001020000100005062149791480002501300131301051300441254983126268300102010000200002010000200001300381300381120021109101001010000100010000000012703162212952510000100001000010010130075130039130039130039130039
3002413003897400013002811941725400101001020000100001020000100005062149791480002501300141301321300571254983126268300102010000200002010000200001300381300381120021109101001010000100010000000012702162212952510000100001000010010130039130039130039130039130039
3002413003897400013002311941725400101001020000100001020000100005062149791480002501300131300791300431254983126268300102010000200002010000200001300381300381120021109101001010000100010000030012704163212952510000100001000010010130039130039130039130039130039
3002413003897404013002311941725400101001020000100001020000100005062149791480002501300131300441300381254983126268300102010000200002010000200001300381300381120021109101001010000100010000000012701163312952510000100001000010010130039130039130039130039130039
3002413007797400013002311941725400101001020000100001020000100005062149791480002511300131300381300381255413126268300102010000200002010000200001300381300381120021109101001010000100010000100012701162212952510000100001000010010130039130039130039130039130039
3002413003897400013002311941725400101001020000100001020000100005062149791480002501300131300961300531254983126268300102010000200002010000200001300381300381120021109101001010000100010000100012702162212952510000100001000010010130039130039130039130039130039
3002413003897400013002311941725400101001020000100001020000100005062149791480002501300131301191300411254983126268300102010000200002010000200001300381300381120021109101001010000100010000000012702162212952510000100001000010010130039130039130039130039130039
3002413003897400013002311941725400181001020000100001020000100005062149791480002501300131300981300571254983126268300102010000200002010000200001300381300381120021109101001010000100010000000012702164312952510000100001000010010130039130039130039130039130039
3002413003897404013002311941725400101001020000100001020000100005062149791480002501300131300401300381254983126268300102010000200002010000200001300381300381120021109101001010000100010000030012703163312952510000100001000010010130039130039130039130039130068

Test 3: throughput

Count: 8

Code:

  fcvtps w0, s8
  fcvtps w1, s8
  fcvtps w2, s8
  fcvtps w3, s8
  fcvtps w4, s8
  fcvtps w5, s8
  fcvtps w6, s8
  fcvtps w7, s8
  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

retire (01)cycle (02)030b191e3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)9fa6a7a8acc5branch mispredict (cb)cdcfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
1602044006431100032252401048010016000410016002050014401321400224004140041199776199921601202001600322001600324004140041118020110099100801001000000111511711600400388000080000801004004240042400424004240042
1602044004131100032252401048010016000410016002050014401321400224004140041199776199921601202001600322001600324004140041118020110099100801001000000111511701600400388000080000801004004240042400424004240042
1602044004131000032252401048010016000410016002050014401320400224004140041199776199921601202001600322001600324004140041118020110099100801001000000111511701600400388000080000801004004240042400424004240042
1602044004131100032252401048010016000410016002050014401320400224004140041199776199921601202001600322001600324004140041118020110099100801001000000111511701600400388000080000801004004240042400424004240042
1602044004131000032252401048010016000410016002050014401321400224004140041199776199921601202001600322001600324004140041118020110099100801001000000111511701600400388000080000801004004240042400424004240042
1602044004131000032252401048010016000410016002050014401321400224004140041199776199921601202001600322001600324004140041118020110099100801001000000111511701611400388000080000801004004240042400424004240042
1602044004131000032252401048010016000410016002050014401321400224004140041199776199921601202001600322001600324004140041118020110099100801001000000111511701600400388000080000801004004240042400424004240042
1602044004131000032252401048010016000410016002050014401321400224004140041199776199921601202001600322001600324004140041118020110099100801001000000111511701610400388000080000801004004240042400424004240042
1602044004131000055252401048010016000410016002050014401321400224004140041199776199921601202001600322001600324004140041118020110099100801001000003111511701600400388000080000801004004240042400424004240042
1602044004131100060252401048010016000410016002050014401321400224004140041199776199921601202001600322001600324004140041118020110099100801001000000111511701600400388000080000801004004240042400424004240042

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

retire (01)cycle (02)03181e3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)5e5f60696b6d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)9fa0a1a8accfd0d2d5d6ddinst fetch restart (de)e0? int output thing (e9)ea? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
1600244005531000482524001080010160000101600005014400000004002204004140041199963200211600102016000020160000400414004111800211091080010100000502000416114003880000080000800104004240042400424004240042
1600244004131000422524001080010160000101600005014400000004002204004140041199963200211600102016000020160000400414004111800211091080010100010502000116224003880000080000800104004240042400424004240042
1600244004131000422524001080010160000101600005014400000004002204004140041199963200211600102016000020160000400414004111800211091080010100010502000116224003880000080000800104004240042400424004240042
1600244004131100422524001080010160000101600005014400001004002204004140041199963200211600102016000020160000400414004111800211091080010100000502000116114003880000080000800104004240042400424004240042
1600244004131000422524001080010160000101600005014400000004002204004140041199963200211600102016000020160000400414004111800211091080010100000502001216114003880000080000800104004240042400424004240042
1600244004131000422524001080010160000101600005014400000004002204004140041199963200211600102016000020160000400414004111800211091080010100000502000116114003880000080000800104004240042400424004240042
16002440041310004225240010800101600001016000050144000000040022040041400411999632002116001020160000201600004004140041118002110910800101000520502000116114003880000080000800104004240042400424004240042
1600244004131000422524001080010160000101600005014400000114002204004140041199963200211600102016000020160000400414004111800211091080010100000502000116114003880000080000800104004240042400424004240042
1600244004131000422524001080010160000101600005014400000004002204004140041199963200211600102016000020160000400414004111800211091080010100000502000116114003880000080000800104004240042400424004240042
1600244004131000422524001080010160000101600005014400000004002204004140041199963200211600102016000020160000400414004111800211091080010100000502000116114003880000080000800104004240042400424004240042