Apple M1 Microarchitecture Research by Dougall Johnson

Firestorm: Overview | Base Instructions | SIMD and FP Instructions
Icestorm:  Overview | Base Instructions | SIMD and FP Instructions

FCVTPS (scalar, S to X)

Test 1: uops

Code:

  fcvtps x0, s0
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 3.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 2.000

retire (01)cycle (02)03191e1f3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch fp/simd (57)huge thing fp/simd (5b)696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op fp/simd (7e)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst integer (97)a0a1a8accfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
2004541400043253000100020002000180005225415412483274200020002000541541111001100000007311611538100010001000542542542542542
2004541400043253000100020002000180005225415412483274200020002000541541111001100000007311611538100010001000542542542542542
2004541400043253000100020002000180005225415412483274200020002000541541111001100000007311611538100010001000542542542542542
2004541400043253000100020002000180005225415412483274200020002000541541111001100000007311611538100010001000542542542542542
2004541500043253000100020002000180005225415412483274200020002000541541111001100000007311611538100010001000542542542542542
2004541400043253000100020002000180005225415412483274200020002000541541111001100000007311611538100010001000542542542542542
2004541400043253000100020002000180005225415412483274200020002000541541111001100000007311611538100010001000542542542542542
2004541400043253000100020002000180005225415412483274200020002000541541111001100000007311611538100010001000542542542542542
2004541400043253000100020002000180005225415412483274200020002000541541111001100000007311611538100010001000542542542542542
20045414021043253000100020002000180005225415412483274200020002000541541111001100000007311611538100010001000542542542542542

Test 2: Latency 1->2 roundtrip

Code:

  fcvtps x0, s0
  fmov d0, x0
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 13.0038

retire (01)cycle (02)03080b0e1e1f3f4f51inst issue (52)~issue int (53)~issue fp/simd (54)~issue ld/st (55)~dispatch int (56)~dispatch fp/simd (57)~dispatch ld/st (58)huge thing int (59)huge thing ld/st (5a)huge thing fp/simd (5b)60696b6d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op ld/st (7d)~map op fp/simd (7e)~map lookup int (7f)~map lookup ld/st (80)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa1a6a8a9acc2branch mispredict (cb)cdcfd0d5d6ddinst fetch restart (de)e0? int output thing (e9)ld/st retires (ed)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
302041300381008000001300231194172540100101002000010000100200001000050062149791480103411300130130038130038125476312624630100200100002000020010000202441301331300381120201100991001010010000100010000000000131012162212952510000100001000010100130042130039130039130039130039
302041300381008000001300231194172540100101002000010000100200001000050062149791480103401300130130038130038125476312624630100200100002000020010000200001300381300401120201100991001010010000100010000000000131012162212952510000100001000010100130039130039130039130039130039
302041300381007000001300231194172540100101002000010000100200001000050062149791480103411300130130038130038125476312624630100200100002000020010000200001300381300381120201100991001010010000100010000000000131012162212952810000100001000010100130039130039130039130039130039
302041300381008000001300231194172540100101002000010000100200001000050062149791480103411300130130038130038125476312624630100200100002000020010000200001300381300381120201100991001010010000100010000000000131012162212952510000100001000010100130039130039130039130039130039
302041300381008000001300231194173440100101002000010000100200001000050062149791480103411300130130038130038125476312624630100200100002000020010000200001300381300381120201100991001010010000100010000000000131012162212952510000100001000010100130039130039130039130039130039
3020413003810080081201300231194172540100101002000010000100200001000050062149791480103411300130130038130038125476312624630100200100002000020010000200001300381300381120201100991001010010000100010000000000131012162212952510000100001000010100130039130039130039130039130039
302041300381008110059813002311941725401251010020003100001172000010000500623431414801034113034301303791300381254762412624630100200100002000020010000200001300381300381120201100991001010010000100010000000000131012162212952510000100001000010100130039130043130041130039130039
302041300381008000001300231194172540100101002000010000100200001000050062149791480103411300130130038130038125476312624630100200100002000020010000200001300381300381120201100991001010010000100010000000000131012172212952510000100001000010100130039130039130039130039130039
302041300381008000001300231194172540100101002000010000100200001000050062149791480103411300130130038130038125476312624630100200100002000020010000200001300381300381120201100991001010010000100010000000000131012162212952510000100001000010100130039130039130039130039130039
302041300381008000001300231194172540100101002000010000100200001000050062149791480103401300130130038130038125476312624630100200100002000020210000200001300381300381120201100991001010010000100410006024276000131012162312990110013100001000010100130039130039130039130039130039

1000 unrolls and 10 iterations

Result (median cycles for code): 13.0038

retire (01)cycle (02)03070b18191e1f3f4f51inst issue (52)~issue int (53)~issue fp/simd (54)~issue ld/st (55)~dispatch int (56)~dispatch fp/simd (57)~dispatch ld/st (58)huge thing int (59)huge thing ld/st (5a)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op ld/st (7d)~map op fp/simd (7e)~map lookup int (7f)~map lookup ld/st (80)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa0a6a8a9acc5cfd2d5d6dbddinst fetch restart (de)e0? int output thing (e9)ld/st retires (ed)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
300241300381007000013050130101119417254001010010200001000010200001000050621497914800025013001313003813004012549831262703001020100002000020100002000013003813004111200211091010010100001001000000001270061601112952510000100001000010010130039130039130039130039130039
300241300381008001011790130023119417254001010010200001000010200001000050621497914800025013001313003813003812549831262683001020100002000020100002000013003813003811200211091010010100001001000010001270011601112952510000100001000010010130039130039130039130039130039
30024130038100800006540130023119417254001010010200001000010200001000050621497914800025013001713003813003812549831262683001020100002000020100002000013004113003811200211091010010100001001000000001270011601112958110000100001000010010130039130075130069130042130039
300241300381008000093013002311941725400101001020000100001020000100005062149791480002501300131300381300381254983126268300102010000200002010000200001300381300381120021109101001010000100100000000127001171361112952510000100001000010010130039130039130039130039130039
300241300381008000013200130023119417254001010010200001000010200001000050621497914800025013001313003813003812549831262883001020100002000020100002000013003813003811200231091010010100001001000000001270011601112952510000100001000010010130039130039130039130039130039
30024130038100800004530130023119417254001010013200001000010200001000050621497914800025113001313003813003812549831262683001020100002000020100002000013003913004011200211091010010100001001000060001270011601112952510000100001000010010130039130039130039130039130039
300241300381008000012870130023119417254001010010200001000010200001000050621497914800025113001313003913003812549831262683001020100002000020100002000013003813003811200211091010010100001001000000001270021601112952510000100001000010010130039130039130087130046130039
300241300381008000000130023119417254001010010200001000010200001000050621497914800025113001313003813003812549831262683001020100002000020100002000013003813003811200211091010010100001001000000001270011601112952510000100001000010010130039130039130039130039130039
300241300381008000012600130023119417254001010010200001000010200001000050621497914800025013001913004113004012549931262683001022100002000020100002000013003813003811200211091010010100001001000000001270011601112952510000100001000010010130039130039130039130039130039
3002413003897400003540130023119417254001010010200001000010200001000050621497914800025013001313003813003812549831262683001020100002000020100002000013003813003811200211091010010100001001000000001270011601112952510000100001000010010130039130039130039130039130039

Test 3: throughput

Count: 8

Code:

  fcvtps x0, s8
  fcvtps x1, s8
  fcvtps x2, s8
  fcvtps x3, s8
  fcvtps x4, s8
  fcvtps x5, s8
  fcvtps x6, s8
  fcvtps x7, s8
  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

retire (01)cycle (02)03080e18191e1f3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)9fa0a1a8a9acc2c5branch mispredict (cb)cdcfd5d6e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
16020440066311000000697252401048010016000410016002050014401321400224004140041199776199921601202001600322001600324004140041118020110099100801001000000001115117116400388000080000801004004240042400424004240042
1602044004131000000032252401048010016000410016002050014401320400224004140041199776199921601202001600322001600324004140041118020110099100801001000010001115117016400388000080000801004004240042400424004240042
1602044004131100000032252412668010016000410016002050014401320400224004140041199776199921601202001600322001600324004140041118020110099100801001000210001115117016400388000080000801004004240042400424004240042
16020440041310000000322524010480100160004100160020500144013204002240041400411997761999216012020016003220016003240041400411180201100991008010010000490001115117016400388000080000801004004240042400424004240042
1602044004131000000032252401048010016000410016002050014401320400224004140041199776199921601202001600322001600324004140041118020110099100801001000000001115117016400388000080000801004004240042400424004240042
1602044004131100000032252401048010016000410016002050014401320400224004140041199776199921601202001600322001600324004140041118020110099100801001000010001115117016400388000080000801004004240042400424004240042
1602044004131000000032252401048010016000410016002050014401320400224004140041199776199921601202001600322001600324004140041118020110099100801001000030001115117016400388000080000801004004240042400424004240042
160204400413110000002221172401048010016000410016002050014401320400224004140041199776199921601202001600322001600324004140041118020110099100801001000040001115117016400388000080000801004004240042400424004240042
1602044004131100000032252401048010016000410016002050014401320400224004140041199776199921601202001600322001600324004140041118020110099100801001000000001115117016400388000080000801004004240042400424004240042
1602044004131000000032252401048010016000410016002050014401320400224004140041199776199921601202001600322001600324004140041118020110099100801001000000001115117016400388000080000801004004240042400424004240042

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

retire (01)cycle (02)03080b18191e1f3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)5f60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)9fa6a8accfd0d5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
160024400433100000004225240010800101600001016000050144000000400224004140041199963200211600102016000020160000400414004111800211091080010100005020041611400388000080000800104004240042400424004240042
1600244004132200002104225240010800101600001016000050144000001400224004140041199963200211600102016000020160000400414016931800211091080010100005020011611400388000080000800104004240042400424004240042
160024400413100000004225240010800101600001016000050144000001400224004140041199963200211600102016000020160000400414004111800211091080010100005020011611400388000080000800104004240042400424004240042
1600244004131100000070725240010800101600001016000050144000001400224004140041199963200211600102016000020160000400414004111800211091080010100065020011611400388000080000800104004240042400424004240042
160024400413100000004225240010800101600001016000050144000001400224004140041199963200211600102016000020160000400414004111800211091080010100005020011611400388000080000800104004240042400424004240042
160024400413100000004225240010800101600001016000050144000001400224004140041199963200211600102016000020160000400414004111800211091080010100005020011611400388000080000800104004240042400424004240042
160024400413100000009825240010800101600001016000050144000001400224004140041199963200211600102016000020160000400414004111800211091080010100105020011611400388000080000800104004240042400424004240042
160024400413100000004225240010800101600001016000050144000001400224004140041199963200211600102016000020160000400414004111800211091080010100005020011611400388000080000800104004240042400424004240042
160024400413110000004225240010800101600001016000050144000001400224004140041199963200211600102016000020160000400414004111800211091080010100005020011611400388000080000800104004240042400424004240042
160024400413100000004225240010800101600001016000050144000001400224004140041199963200211600102016000020160000400414012311800211091080010100105020011611400388000080000800104004240042400424004240042