Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FCVTPS (vector, 2D)

Test 1: uops

Code:

  fcvtps v0.2d, v0.2d
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100430372308225472510001000100039816013018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
100430372406125472510001000100039816013018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
100430372406125472510001000100039816003018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
100430372306125472510001000100039816013018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
100430372306125472510001000100039816013018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
100430372306125472510001000100039816013018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
1004303723010325472510001000100039816013018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
1004303724014525472510001000100039816013018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
100430372406125472510001000100039816013018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
100430372406125472510001000100039816013018303730372414328951000100010003037303711100110000073116112629100030383038303830383038

Test 2: Latency 1->2

Code:

  fcvtps v0.2d, v0.2d
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020430037233000012001032954725101001001000010010000500427716003001830037300372826432874510100200100002001000030037300371110201100991001001000010000071011611296330100001003003830038300383003830038
10204300372330000000612954725101001001000010010000500427716013001830037300372826432874510100200100002001000030037300371110201100991001001000010000071011611296330100001003003830038300383003830038
10204300372320000000612954725101001001000010010000500427716013001830037300372826432874510100200100002001000030037300371110201100991001001000010000071011611296330100001003003830038300383003830038
10204300372330000000612954725101001001000010010000500427716013001830037300372826432874510100200100002001000030037300371110201100991001001000010000071011611296330100001003003830038300383003830038
102043003723300000003462954725101001001000010010000500427716013002030037300372826432874510100200100002001000030037300371110201100991001001000010000071011611296330100001003003830038300383003830038
10204300372330000000612954725101001001000010010000500427716013001830037300372826432874510100200100002001000030037300371110201100991001001000010000071011611296330100001003003830038300383003830038
10204300372330000000612954725101001001000010010000500427716003001830037300372826432874510100200100002001000030037300371110201100991001001000010010071011611296330100001003003830038300383003830038
10204300372320000000612954725101001001000010010000500427716003001830084300372826432874510100200100002001000030037300371110201100991001001000010000071011611296330100001003003830038300383003830038
10204300372330000000612954725101001001000010010000500427716003001830037300372826432874510100200100002001000030037300371110201100991001001000010000071011611297050100001003003830038300383003830038
10204300372320000000612954725101001001000010010000500427716003001830037300372826432874510100200100002001000030037300371110201100991001001000010000071011611296330100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)a9acbbc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0ea? simd retires (ee)? int retires (ef)f5f6f7f8fd
100243003723200072629547251001010100001010000504277160030018300373003728286328767100102010000201000030037300371110021109101010000100000006404165529629010000103003830038300383003830038
10024300372330006129547251001010100001010000504277160030018300373003728286328767100102010000201000030180300371110021109101010000100000006404165629629010000103003830038300383003830038
10024300372330006129547251001010100001010000504277160030018300373003728286328767100102010000201000030037300371110021109101010000100000006405165529629010000103003830038300383003830038
10024300372330006129547251001010100001010000504277160030018300373003728286328767100102010000201000030037300371110021109101010000100000006406164429629010000103003830038300383003830038
10024300372320606129547251001010100001010000504277160030018300373003728286328767100102010000201000030037300371110021109101010000100000006405166529629010000103003830038300713003830038
10024300372320006129547251001010100001010000504277160030018300373003728286328767100102010000201000030037300371110021109101010000100000006404164629629010000103003830038300383003830038
10024300372330006129547251001010100001010000504277160030018300373003728286328767100102010000201000030037300371110021109101010000100000006405165529629010000103003830038300383003830038
10024300372250006129547251001010100001010000504277160030018300373003728286328767100102010000201000030037300371110021109101010000100000006405166629629010000103003830038300383003830038
10024300372250006129547251001010100001010000504277160030018300373003728286328767100102010000201000030037300371110021109101010000100000006404164629629010000103003830038300383003830038
10024300372250006129547251001010100071010000504277160030018300373003728286328767100102010000201000030037300372110021109101010000100000006406166629629010000103003830038300383003830038

Test 3: throughput

Count: 8

Code:

  fcvtps v0.2d, v8.2d
  fcvtps v1.2d, v8.2d
  fcvtps v2.2d, v8.2d
  fcvtps v3.2d, v8.2d
  fcvtps v4.2d, v8.2d
  fcvtps v5.2d, v8.2d
  fcvtps v6.2d, v8.2d
  fcvtps v7.2d, v8.2d
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)181e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80204200571550000072258010810080008100800205006401320200202003920039997769990801202008003220080032200392003911802011009910010080000100000011151183162120036800001002004020040200402004020040
80204200391550000030258010810080008100800205006401320200202003920039997769990801202008003220080032200392003911802011009910010080000100000011151182160020036800001002004020040200402004020040
80204200391560000030258010810080008100800205006401320200202003920039997769990801202008003220080032200392003911802011009910010080000100010011151181161220036800001002004020040200402004020040
80204200391560000030258010810080008100800205006401320200202003920039997769990801202008003220080032200392003911802011009910010080000100003011151181161120036800001002004020040200402004020040
80204200391550000030258050510080008100800205006401320200202003920039997769990801202008003220080032200392003911802011009910010080000100003011151181161220036800001002004020040200402004020040
80204200391550000030258010810080008100800205006401321200202003920039997769990801202008003220080032200392003911802011009910010080000100003011151182162220036800001002004020040200402004020040
80204200391550000030258010810080008100800205006401321200202003920039997769990801202008003220080032200392003911802011009910010080000100010011151181162120036800001002004020040200402004020040
80204200391560000030258010810080008100800205006401321200202003920039997769990801202008003220080032200392003911802011009910010080000100000011151181161220036800001002004020040200402004020040
80204200391550000030258010810080008100800205006401320200202003920039997769990801202008003620080032200392003911802011009910010080000100000011151182162320036800001002004020040200402004020040
80204200391550000030258010810080008100800205006401320200202003920039997769990801202008003220080032200392003911802011009910010080000100000011151180162220036800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
800242005015504025800101080000108000050640000020020200392003999960310019800102080000208000020039200391180021109101080000103305020291623242003680000102004020040200402004020040
8002420039156082258001010800001080000506400001200202003920039999603100198001020800002080000200392003911800211091010800001002705020231625262003680000102004020040200402004020040
8002420039155040258001010800001080000506400000200202003920039999603100198001020800002080000200392003911800211091010800001051005020281616282003680000102004020040200402004020040
8002420039156040258001010800001080000506400000200202003920039999603100198001020800002080000200392003911800211091010800001006605020284813282003680000102004020040200402004020040
800242003915504025800101080000108000050640000120020200392003999960310019800102080000208000020039200391180021109101080000102305020261625152003680000102004020040200402004020040
8002420039155040258001010800001080000506400000200202003920039999603100198001020800002080000200392003911800211091010800001003305020271627272003680000102004020040200402004020040
8002420039155040258001010800001080000506400000200202003920039999603100198001020800002080000200392003911800211091010800001001205020141627142003680000102004020040200402004020040
800242003915508225800101080000108000050640000020020200392003999960310019800102080000208000020039200391180021109101080000102005020271613262003680000102004020040200402004020040
800242003915504025800101080390108000050640000020020200392003999960310019800102080000208000020039200391180021109101080000100005020271631272003680000102004020040200402004020040
8002420039155040258001010800001080000506400000200202003920039999603100198001020800002080000200392003911800211091010800001044005020151625142003680000102004020040200402004020040