Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FCVTPS (vector, 8H)

Test 1: uops

Code:

  fcvtps v0.8h, v0.8h
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100430372438225472510001000100039816003018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
100430372406125472510001000100039816013018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
10043037230612547251000100010003981601301830373037241432895100010001000303730371110011000016573116112629100030383038303830383038
100430372406125472510001000100039816013018303730372414328951000100010003037303711100110001073116112629100030383038303830383038
100430372306125472510001000100039816013018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
100430372306125472510001000100039816013018303730372414328951000100010003037303711100110000373116112629100030383038303830383038
100430372406125472510001000100039816013018303730372414328951000100010003037303711100110000373116112629100030383038303830383038
100430372406125472510001008100039816013018303730372414328951000100010003037303711100110000373116112629100030383038303830383038
100430372306125472510001000100039816013018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
1004303723126125472510001000100039816013018303730372414328951000100010003037303711100110000673116112629100030383038303830383038

Test 2: Latency 1->2

Code:

  fcvtps v0.8h, v0.8h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043003723303173295472510100100100001001000050042771600300183003730037282643287451010020010000200100003003730037111020110099100100100001000371011611296330100001003003830038300383003830038
10204300372320061295472510100100100001001000050042771600300183003730037282643287451010020010000200100003003730037111020110099100100100001000071011611296330100001003003830038300383003830038
10204300372320061295472510100100100001001000050042771600300183003730037282643287451010020010000200100003003730037111020110099100100100001000071011611296330100001003003830038300383003830038
102043003723200673295472510100100100001001000050042771600300183003730037282643287451010020010000200100003003730037111020110099100100100001001071011611296330100001003003830038300383003830038
10204300372330061295472510100100100001001000050042771600300183003730037282643287451010020010000200100003003730037111020110099100100100001000071011611296330100001003003830038300383003830038
10204300372330061295472510100100100001001000050042771600300183003730037282643287451010020010000200100003003730037111020110099100100100001000071011611296330100001003003830038300383003830038
10204300372320061295472510100100100001001000050042771600300183003730037282643287451010020010000200100003003730037111020110099100100100001000071011611296330100001003003830038300383003830038
10204300372330061295472510100100100001001000050042771600300183003730037282643287451010020010000200100003003730037111020110099100100100001000371011611296330100001003003830038300383003830038
10204300372330061295472510100100100001001000050042771600300183003730037282643287451010020010000200100003003730037111020110099100100100001001071011611296330100001003003830038300383003830038
10204300372320061295472510100100100001001000050042771600300183003730037282643287451010020010000200100003003730037111020110099100100100001000071011611296330100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024300372240612954725100101010000101000050427716030018300373003728286328767100102010000201000030037300371110021109101010000100000640416222962910000103003830038300383003830038
10024300372240612954725100101010000101000050427716030018300373003728286328767100102010000201000030037300371110021109101010000100000640216222962910000103003830038300383003830038
10024300372250612954725100101010000101000050427716030018300373003728286328767100102010000201000030037300371110021109101010000100000667216222962910000103003830038300383003830038
10024300372250612954725100101010000101000050427716030018300373003728286328767100102010000201000030037300371110021109101010000100203640216222962910000103003830038300383003830038
10024300832250612954725100101010000101000050427716030018300373003728286328767100102010000201000030037300371110021109101010000100000640216222962910000103003830038300383003830038
10024300372250612954725100101010000101000050427716030018300373003728286328767100102010000201000030037300371110021109101010000100000640216222962910000103003830038300383003830038
10024300372250612954725100101010000101000050427716030018300373003728286328767100102010000201000030037300371110021109101010000100000640216222962910000103003830038300383003830038
10024300372250612954725100101010000101000050427716030018300373003728286328767100102010000201000030037300371110021109101010000100000640216222962910000103003830038300383003830038
10024300372250822954725100101010000101000050427716030018300373003728286328767100102010000201000030037300371110021109101010000100000640216222962910000103003830038300383003830038
1002430037225026802954725100101010000101000050427716030018300373003728286328767100102010000201000030037300371110021109101010000100000640216222962910000103003830038300383003830038

Test 3: throughput

Count: 8

Code:

  fcvtps v0.8h, v8.8h
  fcvtps v1.8h, v8.8h
  fcvtps v2.8h, v8.8h
  fcvtps v3.8h, v8.8h
  fcvtps v4.8h, v8.8h
  fcvtps v5.8h, v8.8h
  fcvtps v6.8h, v8.8h
  fcvtps v7.8h, v8.8h
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
802042003915500030258010810080008100800205006401321200202003920039997769990801202008003220080032200392003911802011009910010080000100000011151180160020036800001002004020040200402004020040
8020420039155015030258010810080008100800205006401321200202003920039997769990801202008003220080032200392003911802011009910010080000100000011151180160020036800001002004020040200402004020040
802042003915500030258010810080008100800205006401320200202003920039997769990801202008003220080032200392003911802011009910010080000100000011151180160020036800001002004020040200402004020040
80204200391560120302680116100800161008002850064019602002920048200489976109986801282008003820080038200482004811802011009910010080000100003022251281231120045800001002004920049200502004920049
80204200481550120446278011610080016100800285006401960200292009820049997699986801282008003820080038200482004811802011009910010080000100003022251281231120046800001002004920049200502005020049
802042004815503064278021510080016100800285006401961200292004920048997699986801282008003820080038200482004811802011009910010080000100003022251281231120046800001002004920049200492004920049
80204200481560006426801161008001610080028500640196020029200492004810012910176808472008003820080038200482004811802011009910010080000100000222251291231120045800001002004920049200492005020049
8020420048155060642780116100800161008002850064019612002920048200489976109986801282008003820080038200482004811802011009910010080000100013022251281231120045800001002004920049200492004920049
8020420048155000742780116100800161008002850064019602002920048200499976109986801282008003820080038200482004811802011009910010080000100000022251282231120046800001002004920050200502004920050
802042004815500064268011610080016100800285006401960200292004820048997699986801282008003820080038200482004811802011009910010080000100000022251281231120045800001002004920049200492004920050

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8002420051155004025800101080000108000050640000120020200392003999963100198001020800002080000200392003911800211091010800001000000005020616542003680000102004020040200402004020040
8002420039163604025800101080098108000050640784120061200392003999963100198001020800002080000200392003911800211091010800001004100405020716882003680000102004020040200402004020040
80024200391561504025800101080000108000050640000120020200392003999963100198001020800002080000200392003911800211091010800001000000005020516782003680000102004020040200402004020040
8002420039155004025800101080000108000050640000120020200392003999963100198001020800002080000200392003911800211091010800001000000005020516582003680000102004020040200402004020040
8002420039155182644025800101080000108000050640000120020200392003999963100198001020800002080000200392003911800211091010800001000000005020516852003680000102004020040200402004020040
8002420039155004025800101080000108000050640000020020200392003999963100198001020800002080000200392003911800211091010800001000003005020516552003680000102004020040200402004020040
80024200391561204025800101080000108000050640000120020200392003999963100198001020800002080000200392003911800211091010800001000100005020816852003680000102004020197200402004020040
80024202461559010725800101080000108000050640000120020200392003999963100198001020800002080000200392003911800211091010800001000000015020516582003680000102004020040200402004020040
800242003915500402580010108000010801045064083612002020039200399996310019800102080000208000020346201152180021109101080000104002785005037516882003680000102004020040200402004020040
80024200391551204025800101080000108000050640000120020200392003999963100198001020800002080000200392003911800211091010800001000000005020516582003680000102004020040200402004020040