Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FCVTPU (scalar, D to D)

Test 1: uops

Code:

  fcvtpu d0, d0
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)91inst simd alu (9a)acc3cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10043037231261254725100010001000398160030183037303724143289510001000100030373037111001010000091216222629100030383038303830383038
1004303722061254725100010001000398160030183037303724143289510001000100030373037111001010000073216222629100030383038303830383038
10043037232761254725100010001000398160030183037303724143289510001000100030373037111001010000073216222629100030383038303830383038
10043037233661254725100010001000398160030183037303724143289510001000100030373037111001010000073216222629100030383038303830383038
10043037225461254725100010001000398160030183037303724143289510001000100030373037111001010000073216222629100030383038303830383038
1004303723061254725100010001000398160030183037303724143289510001000100030373037111001010000073216222629100030383038303830383038
1004303722061254725100010001000398160030183037303724143289510001000100030373037111001010000073216222629100030383038303830383038
100430372296125472510001000100039816003018303730372414328951000100010003037303711100101000108073216222629100030383038303830383038
1004303723961254725100010001000398160030183037303724143289510001000100030373037111001010000073216222629100030383038303830383038
1004303723361254725100010001000398160030183037303724143289510001000100030373037111001010000073216222629100030383038303830383038

Test 2: Latency 1->2

Code:

  fcvtpu d0, d0
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)191e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043003723300061295472510100100100001001000050042771600300183003730037282643287451010020010000200100003003730037111020110099100100100001000000071011611296330100001003003830038300383003830038
10204300372330030673295472510100100100001001000050042771600300183003730037282643287631010020010000200100003003730037111020110099100100100001000000071011611296330100001003003830038300383003830038
102043003723200061295472510100100100001001000050042771600300183003730037282643287451010020010000200100003003730037111020110099100100100001000000071011611296330100001003003830038300383003830038
1020430037233004561295472510100100100001001000050042771600300183003730037282643287451010020010000200100003003730037111020110099100100100001000000071011611296330100001003003830038300383003830038
102043003723300061295472510100100100001001000050042771600300183003730037282643287451010020010000200100003003730037111020110099100100100001000000071011611296330100001003003830038300383003830038
102043003723300061295472510100100100001001000050042771600300183003730037282643287451010020010000200100003003730082111020110099100100100001002412758071011611296330100001003003830038300383003830038
102043003723300061295472510100100100001001000050042771600300183003730037282643287451010020010000200100003003730037111020110099100100100001000000071011611296330100001003003830038300383003830038
1020430037232000103295472510100100100001001000050042771600300183003730037282643287451010020010000200100003003730037111020110099100100100001000000071011611296330100001003003830038300383003830038
102043003723300061295472510100100100001001000050042771600300183003730037282643287451010020010000200100003003730037111020110099100100100001000000071011611296330100001003003830038300383003830038
102043003723200061295472510100100100001001000050042771600300183003730037282643287451010020010000200100003003730037111020110099100100100001000000071011611296330100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)0318191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)a9acc2cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024300372810000061295472510010101000010100005042771600300180300373003728286328767100102010000201000030037300371110021109101010000100000006402162229629010000103003830038300383003830038
10024300372260000061295472510010101000010100005042771600300180300373003728286328767100102010000201000030037300371110021109101010000100000006402162229629010000103003830038300383003830038
10024300372240000061295472510010101000010100005042771600300180300373008528286328767100102010000201000030037300371110021109101010000100000006402162229629010000103003830038300383003830038
1002430037224001590061295382510010101000010100005042771600300180300373003728286328767100102010000201000030037300371110021109101010000100000006402162229916010000103003830038300383003830038
100243003722500603520612954725100101010000101000050427716003005503003730037282863287671001020100002010000300373003711100211091010100001000221006402162229629010000103003830038300383003830038
100243003724100001257295472510010101000010100005042771600300180300703003728286328767100102010000201000030037302241110021109101010000102000006402162229629010000103013130038300383003830038
100243003722400000220295472510010101000010100005042771601300180300373003728286328767100102010000201000030037300371110021109101010000100000006402162229629010000103003830038300383003830038
10024300372240000061295472510010101000010100005042771601300180300373003728286328767100102010000201000030037300372110021109101010000100000006402162229667010000103003830038300383003830038
10024300372250000061295472510010101000010100005042771601300180300373003728286328767101622010000201000030226300371110021109101010000100000006402162229629010000103003830038300383003830038
100243003722500210061295472510010101000010100005042771600300180300373003728286328767100102210000201000030037300371110021109101010000100000006402162229629010000103003830085300853018030038

Test 3: throughput

Count: 8

Code:

  fcvtpu d0, d8
  fcvtpu d1, d8
  fcvtpu d2, d8
  fcvtpu d3, d8
  fcvtpu d4, d8
  fcvtpu d5, d8
  fcvtpu d6, d8
  fcvtpu d7, d8
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80204200681500302580108100800081008002050064013202002020039200399977699908012020080032200800322003920039118020110099100100800001000070011151180160020036800001002004020040200402004020040
80204200391550302580108100800081008002050064013202002020039200399977699908012020080032200800322003920039118020110099100100800001000060911151180160020036800001002004020040200402004020040
8020420039155011425801081008000810080020500640132020020200392003999773399908012020080036200800382003920039118020110099100100800001000030011151180160020036800001002004020040200402004020040
80204200391550302580108100800081008002050064013202002020039200399977699908012020080032200800322003920039118020110099100100800001000010022251281231120045800001002005020049200492004920049
80204200481500852780116100800161008002850064019602002920049200489976999868012820080038200800382004820048118020110099100100800001000000022251281231120046800001002004920049200492004920050
802042004815006427801161008001610080028500640196020029200492004899761099868012820080038200800382004820048118020110099100100800001000000022251281231120045800001002005020049200492004920049
8020420048160064278011610080016100800285006401961200292004920090997610998680128200800382008003820048200481180201100991001008000010000510022251281231120045800001002005020050200502005020049
80204200481500642780116100800161008002850064019602002920048200489976999868012820080038200800382004820048118020110099100100800001000002322251291231120045800001002004920049200492004920050
8020420048150064278011610080016100800285006401961200292004820048997699986801282008003820080038200482004811802011009910010080000100006016822251281231120045800001002004920049200502004920049
8020420049150064268011610080016100800285006401960200292004820048997610998680128200800382008003820048200481180201100991001008000010000250022251281231120045800001002004920049200492004920049

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)191e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200391501004025800101080000108000050640000200202003920039999631001980010208000020800002003920039118002110910108000010000005037416112003680000102004020040200402004020040
800242003915000214025800101080000108000050640000200612003920039999631001980010208000020800002003920039118002110910108000010000005020216112003680000102004020040200402004020040
800242003915000274025800101080000108000050640000200202003920039999631001980010208000020800002003920039118002110910108000010000005020116112003680000102004020040200402004020040
800242003915000244025800101080000108000050640000200202009120039999631001980010208000020800002003920039118002110910108000010000005020116112003680000102004020040200402004020040
8002420039150002884025800101080000108000050640000200202003920039999631001980010208000020800002003920039118002110910108000010000005020116112003680000102004020040200402004020040
800242003915000124025800101080000108000050640000200202003920039999631001980010208000020800002003920039118002110910108000010000005020116112003680000102004020040200402004020040
800242003915000921125800101080000108000050640000200202003920039999631001980010208000020800002003920039118002110910108000010000005020116112003680000102004020040200402004020040
800242003915000214025800101080000108000050640000200202003920039999631001980010208000020800002003920039118002110910108000010000005020116112003680000102004020095200402004020040
800242003915000051525800101080000108000050640000200202003920039999631001980010208000020800002003920039118002110910108000010000005020116112003680000102004020040200402004020040
8002420039150003274025800101080000108000050640000200202003920039999631001980010208000020800002003920039118002110910108000010000005020116112003680000102004020040200402004020040