Firestorm: FCVTPU (scalar, D to W) measurements

Code:

  fcvtpu w0, d0

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 3.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 2.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
2004	541	4	0	43	25	3000	1000	2000	2000	18000	0	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	73	1	16	1	1	538	1000	1000	1000	542	542	542	542	542
2004	541	5	0	43	25	3000	1000	2000	2000	18000	0	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	73	1	16	1	1	538	1000	1000	1000	542	542	542	542	542
2004	541	5	6	43	25	3000	1000	2000	2000	18000	0	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	73	1	16	1	1	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	43	25	3000	1000	2000	2000	18000	0	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	73	1	16	1	1	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	43	25	3000	1000	2000	2000	18000	0	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	73	1	16	1	1	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	43	25	3000	1000	2000	2000	18000	0	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	73	1	16	1	1	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	43	25	3000	1000	2000	2000	18000	0	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	73	1	16	1	1	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	43	25	3000	1000	2000	2000	18000	0	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	73	1	16	1	1	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	43	25	3000	1000	2000	2000	18000	0	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	73	1	16	1	1	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	43	25	3000	1000	2000	2000	18000	0	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	73	1	16	1	1	538	1000	1000	1000	542	542	542	542	542

Test 2: Latency 1->2 roundtrip

Code:

  fcvtpu w0, d0
  fmov d0, x0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 13.0038

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	77	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30204	130038	974	0	0	0	0	0	0	0	130023	119455	25	40100	10100	20000	10000	100	20000	10000	526	6214979	14801034	0	130013	0	130038	130038	125483	6	126241	0	30100	200	10002	20006	200	10002	20006	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	2	1	1	1	1318	0	1	16	1	1	129534	10000	10000	10000	10100	130039	130039	130039	130042	130039
30204	130038	974	0	0	1	2	1	156	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6215027	14801034	0	130013	0	130038	130038	125476	3	126246	0	30100	200	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	0	0	1310	1	3	16	2	2	129525	10000	10000	10000	10100	130039	130363	130039	130039	130042
30204	130038	974	0	0	0	0	0	0	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	0	130013	0	130038	130038	125476	3	126249	0	30100	200	10000	20611	206	10186	20000	130118	130038	1	1	20201	100	99	100	10100	10000	100	0	10007	0	4283	0	0	0	0	1310	1	2	16	3	3	129525	10000	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	974	0	0	0	0	0	0	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	0	130017	0	130038	130038	125476	3	126246	0	30100	200	10000	20000	200	10000	20000	130519	130038	2	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	0	0	1310	1	2	16	3	2	129525	10000	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	974	0	0	0	0	0	12	0	130023	119417	32	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	0	130013	0	130038	130038	125476	3	126246	0	30100	200	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	0	0	1310	1	2	16	2	3	129525	10000	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	974	0	0	0	0	0	0	0	130023	119418	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	0	130013	0	130038	130038	125476	3	126246	0	30100	200	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	0	0	1310	1	2	16	2	3	129525	10000	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	974	0	0	0	0	0	0	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	0	130013	0	130038	130038	125476	3	126246	0	30100	200	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	10000	3	0	0	0	0	0	1310	1	3	16	3	2	129525	10000	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	974	0	0	0	0	0	0	0	130023	119436	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	0	130013	0	130038	130038	125476	3	126246	0	30100	200	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	0	0	1310	1	3	16	2	2	129525	10000	10000	10000	10100	130039	130070	130039	130039	130039
30204	130038	974	0	0	0	0	0	0	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	0	130013	0	130038	130038	125476	3	126246	0	30100	200	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	0	0	1310	1	3	16	2	2	129597	10000	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	974	0	0	0	0	0	0	0	130278	119417	25	40100	10100	20000	10000	100	20000	10000	500	6215027	14801034	0	130087	0	130038	130039	125476	3	126246	0	30100	200	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	0	0	1310	1	2	16	2	2	129586	10000	10000	10000	10100	131396	131028	130696	132279	132386

1000 unrolls and 10 iterations

Result (median cycles for code): 13.0038

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30024	130038	974	0	0	0	0	0	0	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	0	1	130013	130038	130043	125498	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	0	0	10000	10	0	0	0	0	1270	0	0	0	2	16	0	4	0	1	1	129525	10000	10000	10000	10010	130039	130040	130039	130039	130039
30024	130038	974	0	0	0	0	0	0	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800367	0	1	130085	130038	130038	125500	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	0	1270	0	0	0	1	16	0	0	0	1	1	129525	10000	10000	10000	10010	130039	130039	130039	130039	130039
30024	130038	974	0	0	0	0	0	0	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	0	0	130014	130038	130038	125498	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	0	1270	0	0	0	1	16	0	0	0	1	1	129525	10000	10000	10000	10010	130041	130039	130039	130137	130039
30024	130038	974	0	0	0	0	0	0	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	0	0	130013	130038	130038	125498	3	126271	30010	20	10000	20000	20	10000	20000	130038	130093	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	0	1270	0	0	0	1	16	0	0	0	1	1	129610	10000	10000	10000	10010	130039	130039	130039	130039	130039
30024	130038	974	0	0	0	0	0	0	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	0	0	130013	130038	130038	125498	3	126268	30010	20	10000	20000	20	10065	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	0	1270	0	0	0	1	16	0	0	0	1	1	129525	10000	10000	10000	10010	130039	130039	130039	130039	130041
30024	130038	974	0	0	0	0	0	0	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	0	0	130013	130038	130038	125498	3	126268	30010	20	10000	20246	20	10062	20000	130083	130093	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	0	1270	0	0	0	1	16	0	0	0	2	1	129525	10000	10000	10000	10010	130039	130039	130039	130039	130039
30024	130038	974	0	0	0	0	0	0	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	0	1	130013	130038	130129	125499	3	126268	30010	20	10000	20000	20	10000	20000	130038	130078	1	1	20021	10	9	10	10010	10000	10	0	0	10000	1	0	4288	0	0	1270	0	0	0	1	16	0	0	0	1	1	129525	10000	10000	10000	10010	130066	130042	130039	130039	130039
30024	130038	974	0	0	0	0	0	0	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	0	0	130013	130038	130038	125498	3	126268	30010	20	10000	20000	20	10000	20000	130062	130039	1	1	20021	10	9	10	10010	10000	10	0	0	10000	0	0	0	0	0	1270	0	0	0	1	16	0	0	0	1	2	129525	10000	10000	10000	10010	130039	130039	130039	130039	130039
30024	130038	974	0	0	0	0	0	0	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	0	1	130013	130038	130038	125536	3	126268	30010	20	10000	20131	20	10000	20000	130038	130084	1	1	20021	10	9	10	10010	10000	10	2	2	10013	1	2	18748	0	0	1270	0	0	0	1	16	0	0	0	1	1	129525	10000	10000	10000	10010	130039	130039	130039	130039	130039
30024	130038	974	0	0	0	0	0	0	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6215699	14806589	0	0	130015	130038	130038	125522	9	126268	30180	20	10000	20000	20	10000	20240	130373	130144	2	1	20021	10	9	10	10010	10000	10	0	0	10000	4	0	9	12	0	1270	0	0	0	1	16	0	0	1	1	1	129525	10000	10000	10000	10010	130039	130039	130039	130039	130039

Test 3: throughput

Count: 8

Code:

  fcvtpu w0, d8
  fcvtpu w1, d8
  fcvtpu w2, d8
  fcvtpu w3, d8
  fcvtpu w4, d8
  fcvtpu w5, d8
  fcvtpu w6, d8
  fcvtpu w7, d8

Initialization

  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst ldst (9b)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	eb	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	40064	300	0	507	25	240104	80100	160004	100	160020	500	1440132	1	40022	40041	40041	19977	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	0	100	0	0	0	1	1	1	5117	0	16	0	0	40038	80000	0	80000	80100	40042	40042	40042	40042	40042
160204	40041	300	0	32	25	240104	80100	160004	100	160020	500	1440132	1	40022	40041	40041	19977	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	0	100	0	0	0	1	1	1	5117	0	16	0	0	40038	80000	0	80000	80100	40042	40042	40042	40042	40042
160204	40041	300	0	32	25	240104	80100	160004	100	160020	500	1440132	1	40022	40041	40041	19977	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	0	100	0	0	0	1	1	1	5117	0	16	0	0	40038	80000	0	80000	80100	40042	40042	40042	40042	40042
160204	40041	300	0	32	25	240104	80100	160004	100	160020	500	1440132	1	40022	40041	40041	19977	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	0	100	0	0	0	1	1	1	5117	0	16	0	0	40038	80000	0	80000	80100	40042	40042	40042	40042	40042
160204	40041	300	0	32	25	240104	80100	160004	100	160020	500	1440132	1	40022	40041	40041	19977	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	0	100	0	0	0	1	1	1	5117	0	16	0	0	40038	80000	0	80000	80100	40042	40042	40042	40042	40042
160204	40041	300	0	32	25	240104	80100	160004	100	160020	500	1440132	1	40022	40041	40041	19977	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	0	100	0	0	0	1	1	1	5117	0	16	0	0	40038	80000	0	80000	80100	40042	40042	40042	40042	40042
160204	40041	300	0	32	25	240104	80100	160004	100	160020	500	1440132	1	40022	40041	40041	19977	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	0	100	0	0	0	1	1	1	5117	0	16	0	0	40038	80000	0	80000	80100	40042	40042	40042	40042	40042
160204	40041	300	0	32	25	240104	80100	160004	100	160020	500	1440132	1	40022	40041	40041	19977	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	0	100	0	0	0	1	1	1	5117	0	16	0	0	40038	80000	0	80000	80100	40042	40042	40042	40042	40042
160204	40041	300	0	32	25	240104	80100	160004	100	160020	500	1440132	1	40022	40041	40360	19977	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	0	100	0	0	0	1	1	1	5117	0	16	0	0	40038	80000	0	80000	80100	40042	40042	40042	40042	40042
160204	40041	300	0	32	25	240104	80100	160004	100	160020	500	1440132	1	40022	40041	40041	19977	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	0	100	0	0	0	1	1	1	5117	0	16	0	0	40038	80000	0	80000	80100	40042	40042	40042	40042	40042

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d cache writeback (a8)	ac	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	da	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	40055	311	0	0	0	42	25	240010	80010	160000	10	160000	50	1440000	0	0	40022	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	5020	0	0	0	2	16	0	1	1	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	311	0	0	0	70	25	240010	80010	160000	10	160000	50	1440000	1	1	40022	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40128	1	1	80021	10	9	10	80010	10	0	0	5038	0	0	0	2	16	0	1	1	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	310	0	3	0	137	25	240010	80010	160000	10	160000	50	1440000	1	0	40033	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	5020	0	0	0	1	16	0	1	1	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	311	0	0	0	42	25	240010	80010	160000	10	160000	50	1440000	0	0	40022	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	5020	0	0	0	1	16	0	1	1	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	321	0	0	0	42	25	240010	80010	160000	10	160000	50	1440000	0	0	40022	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	5020	0	0	0	2	16	0	1	1	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	321	0	0	0	213	25	240272	80303	160000	10	160000	50	1440000	1	1	40022	40041	40041	20019	3	20021	160010	20	160000	20	160214	40041	40041	2	1	80021	10	9	10	80010	10	0	0	5020	3	0	0	1	16	0	1	1	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	310	0	0	0	140	25	240010	80010	160000	10	160000	50	1440000	0	0	40022	40041	40041	19996	3	20021	160010	20	160000	20	160200	40041	40041	1	1	80021	10	9	10	80010	10	0	0	5020	0	0	0	1	16	0	1	1	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	310	0	0	0	84	25	240010	80010	160000	10	160000	50	1440000	0	0	40022	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	5020	0	0	0	1	16	0	1	1	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	310	0	12	0	42	25	240010	80010	160000	10	160000	50	1440000	0	0	40022	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	5020	0	0	0	2	16	0	1	1	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	310	0	0	0	42	25	240010	80010	160000	10	160000	50	1440000	0	0	40022	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	6	5020	0	0	0	1	44	0	1	1	40038	80000	80000	80010	40042	40042	40042	40042	40042

FCVTPU (scalar, D to W)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations