Apple M1 Microarchitecture Research by Dougall Johnson

Firestorm: Overview | Base Instructions | SIMD and FP Instructions
Icestorm:  Overview | Base Instructions | SIMD and FP Instructions

FCVTPU (scalar, D to X)

Test 1: uops

Code:

  fcvtpu x0, d0
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 3.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 2.000

retire (01)cycle (02)031e3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch fp/simd (57)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op fp/simd (7e)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst integer (97)a8accfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
2004541404325300010002000200018000152254154124832742000200020005415411110011000007311611538100010001000542542542542542
2004541404325300010002000200018000052254154124832742000200020005415411110011000007311611538100010001000542542542542542
2004541404325300010002000200018000052254154124832742000200020005415411110011000007311611538100010001000542542542542542
2004541408525300010002000200018000052254154124832742000200020005415411110011000007311611538100010001000542542542542542
2004541404325300010002000200018000152254154124832742000200020005415411110011000007311611538100010001000542542542542542
20045415304325300010002000200018000052254154124832742000200020005415411110011000007311611538100010001000542542542542542
2004541404325300010002000200018000052254154124832742000200020005416231110011000007311611538100010001000542542542542542
2004541404325300010002000200018000052254154124832742000200020005415411110011000007311611538100010001000542542542542542
2004541464325300010002000200018000052254154124832742000200020005415411110011000007311611538100010001000542542542542542
20045414184325300010002000200018000052254154124832742000200020005415411110011000007311611538100010001000542542542542542

Test 2: Latency 1->2 roundtrip

Code:

  fcvtpu x0, d0
  fmov d0, x0
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 13.0038

retire (01)cycle (02)03080b18191e1f3a3f4f51inst issue (52)~issue int (53)~issue fp/simd (54)~issue ld/st (55)~dispatch int (56)~dispatch fp/simd (57)~dispatch ld/st (58)huge thing int (59)huge thing ld/st (5a)huge thing fp/simd (5b)60696b6d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op ld/st (7d)~map op fp/simd (7e)~map lookup int (7f)~map lookup ld/st (80)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa6a8acc2c5branch mispredict (cb)cdcfd0d5d6ddinst fetch restart (de)e0? int output thing (e9)ld/st retires (ed)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
302041300409740000000130023119417254010010100200001000010020000100005006214979148010340130013013003813003812548361262423010020010002200062001000220006130038130038112020110099100101001000010010000000111131701161112953410000100001000010100130039130039130039130039130039
302041300389740000000130023119417254010010100200001000010020000100005006214979148010340130013013003813003812548361262423010020010002200062001000220006130038130038112020110099100101001000010010000000111131701161212953310000100001000010100130039130039130039130039130039
302041300389740000000130023119417254010010100200001000010020000100005006214979148010340130013013003813003812547631262463010020010000200002001000020000130038130038112020110099100101001000010010000000000131012163312952510000100001000010100130039130039130039130039130039
302041300389740000000130023119417254010010100200001000010020000100005006214979148010340130013013003813003812547631262463010020010000200002001000020000130038130038112020110099100101001000010010000000010131012163312952510000100001000010100130039130039130039130039130039
302041300389740000000130023119417254010010100200001000010020000100005006214979148010340130013013003813003812547631262463010020010000200002001000020000130038130038112020110099100101001000010010000000000138512162212952510000100001000010100130039130039130039130039130039
302041300389740000000130023119417254010010100200001000010020000100005006214979148010340130013013003813003812547631262463010020010000200002001000020000130073130058112020110099100101001000010010000000000131012162212956910000100001000010100130039130039130039130039130039
302041300389740000000130023119417254010010100200001000010020000100005006214979148010340130013013003813003812547631262463010020010000200002001000020000130038130038112020110099100101001000010010000000000131012163212952510000100001000010100130039130039130039130039130039
3020413003897400009600130023119417254010010100200001000010020000100005006214979148010340130013013007413003812551231262463010020010000200002001000020000130038130038112020110099100101001000010010000000000131013162312952510000100001000010100130039130039130039130039130039
302041300389750000000130023119417254010010100200001000010020000100005006214979148010340130013013003813003812547631262463010020010000200002001000020000130038130038112020110099100101001000010010000000000131012162312952510000100001000010100130039130039130039130039130039
302041300389740000000130023119417254010010100200001000010020000100005006214979148010340130013013003813003812547631262463010020010000200002001000020000130038130038112020110099100101001000010010000000100138911162312952710007100001000010100130039130039130039130039130039

1000 unrolls and 10 iterations

Result (median cycles for code): 13.0038

retire (01)cycle (02)030818191e3f4f51inst issue (52)~issue int (53)~issue fp/simd (54)~issue ld/st (55)~dispatch int (56)~dispatch fp/simd (57)~dispatch ld/st (58)huge thing int (59)huge thing ld/st (5a)huge thing fp/simd (5b)5f60696b6d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op ld/st (7d)~map op fp/simd (7e)~map lookup int (7f)~map lookup ld/st (80)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa1a6a8a9acc2c5branch mispredict (cb)cfd2icache miss (d3)d5d6ddinst fetch restart (de)e0? int output thing (e9)eaecld/st retires (ed)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
30024130038974000241300231194172540010100102000010000102000010000506214979148000250013001301300381300381254983126268300102010000200002010000200001300381300381120021109101001010000100100000000001270002161112952510000160100001000010010130039130039130039130039130039
300241300389740000130023119417254001010010200001000010200001000050621497914800025001300130130038130038125498312627130010201000020000201000020000130038130040112002110910100101000010010000000000127000116111295251000000100001000010010130039130039130043130039130039
300241300389730000130023119417254001010010200001000010200001000050621497914800025001300130130038130038125498312626830010201006620000201000020000130038130038112002110910100101000010010000000000127000116111295251000000100001000010010130039130039130039130039130039
300241300389740000130023119417254001010010200001000010200001000050621497914800025111300130130038130038125498312626830010201000020000201000020000130038130038112002110910100101000010010000000000127000116111295251000000100001000010010130039130039130039130039130039
300241300399740000130023119417254001010010200001000010200001000050621497914800025011300130130038130041125498312626830010201000020000201000020000130043130049112002110910100101000010010000000000127000116111295251000000100001000010010130039130039130039130039130039
300241300389740000130023119417254001010010200001000010200001000050621497914800025011300130130038130038125498312626830010201000020000201000020000130038130038112002110910100101000010010000106000127000116111295251000000100001000010010130039130039130039130043130039
3002413003897400096130023119417254001010014200001000010200001000050621497914800025011300130130038130038125498312626830010201000020000201000020000130038130038112002110910100101000010010000000000127000116111295251000000100001000010010130039130039130039130039130039
300241300389740000130023119422254001010010200001000010200001000050621497914800025001300130130038130039125498312626830010201000020000201000020000130038130038112002110910100101000010010000100000127000116111295251000000100001000010010130069130039130039130039130039
3002413003897400001300231194172540010100102000010000102000010000506214979148000250013001301300381300381254983126268300102010000200002010000200001300381301171120021109101001010000100100000024010127000116111295251000000100001000010010130039130039130039130039130039
300241300389740009130023119417254001010010200001000010200001000050621497914800025011300130130038130038125498312626830010201000020000201000020000130038130038112002110910100101000010010000000000127000216111295251000000100001000010010130039130124130039130039130122

Test 3: throughput

Count: 8

Code:

  fcvtpu x0, d8
  fcvtpu x1, d8
  fcvtpu x2, d8
  fcvtpu x3, d8
  fcvtpu x4, d8
  fcvtpu x5, d8
  fcvtpu x6, d8
  fcvtpu x7, d8
  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

retire (01)cycle (02)030b181e1f3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)9fa1a6a8acc5branch mispredict (cb)cdcfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
1602044006630000003225240104801001600041001600205001440132400224004140041199776199921601202001600322001600324004140123118020110099100801001000000111511701600400388000080000801004004240042400424004240042
1602044004130000003225240104801001600041001602365001440132400224004140041199776199921601202001600322001600324004140041118020110099100801001000000111511701600400388000080000801004004240042400424004240042
1602044004130000003225240104801001600041001600205001440132400224004140041199776199921601202001600322001600324004140041118020110099100801001000000111511701600400388000080000801004004240042400424004240042
1602044004130000003225240104801001600041001600205001440132400224004140041199776199921601202001600322001600324004140041118020110099100801001000000111511701600400388000080000801004004240042400424004240042
1602044004130000907425240104801001600041001600205001440132400224004140041199776199921601202021600322001600324004140041118020110099100801001000000111511701600400388000080000801004004240042400424004240042
1602044004129900003225240104801001600041001600205001440132400224004140124199776199921601202001600322001600324004140041118020110099100801001000003111511701600400388000080000801004004240042400424004240042
1602044004130000003225240104801001600041001600205001440132400224004140041199776199921601202001600322001600324004140041118020110099100801001000000111511711600400388000080000801004004240042400424004240042
16020440041300000032252401048010016000410016020050014401324002240041400412000214200801601202001600322001600324004140041118020110099100801001000003111511701600400388000080000801004004240042400424004240042
1602044004129900003225240104801001600041001600205001440132400224004140041199776199921601202001600322001600324004140041118020110099100801001000000111511701600400388000080000801004004240042400424004240042
1602044004130000003225240104801001600041001600205001440132400224004140041199776199921601202001600322001600324004140041118020110099100801001000000111511701600400388000080000801004004240042400424004240042

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

retire (01)cycle (02)0308090a0b181e3a3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)5f6061696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)9fa0a1a6a8acc2cfd0d2d5d6dbddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
160024400423000000012094325240010800101600001016000050144000000040022400414004119996320021160010201600002016000040041400411180021109108001010002130502053416043400388000080000800104004240042400424004240042
160024400413000000012023825240010800101600001016000050144000000040022400414004119996320021160010201600002016000040041400411180021109108001010000000502050416034400388000080000800104004240042400424004240042
1600244004130000000004225240010800101600001016000050144709601540022400414004119996320021160010201600002016000040041400411180021109108001010005300502054816043400388000080000800104004240042400424004240042
1600244004129900000004225240010800101600001016000050144736600040022400414004119996320021160814201600002016000040041400415180021109108001010000000502000416076403008000080000800104004240042400424004240042
16002440041300000000042252400108001016000010160000501440000000400224004140041199962620021160010201600002016000040041400411180021109108001010000000502000516034400388000080000800104004240042400424004240042
16002440041300000000061225240010800101600001016000050144000001540022400414004119996320021160010201600002016000040041400411180021109108001010000000502000316034400388000080000800104004240042400424004240042
16002440041299000001504225240010800101600001016000050144000000040022400414004119996320021160010201600002016000040041400411180021109108001010000000502000616043400388000080000800104004240042400424004240042
16002440041300000000070725240010800101600001016000050144000000040022400414004119996320021160010201600002016000040041400411180021109108001010000000502000616067400388000080000800104004240042400424004240042
1600244004130000000004225240010800101601961016000050144000001040022400414004119996320021160010201600002016000040041400411180021109108001010000000502000616064400388000080000800104004240042400424004240042
1600244004130000000004225240010800101600001016000050144000000040022400414004119996320021160010201600002016000040041400411180021109108001010000130502000416064400388000080000800104004240042400424004240042