Firestorm: FCVTPU (scalar, D to X) measurements

Code:

  fcvtpu x0, d0

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 3.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 2.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
2004	541	4	0	43	25	3000	1000	2000	2000	18000	1	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	73	1	16	1	1	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	43	25	3000	1000	2000	2000	18000	0	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	73	1	16	1	1	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	43	25	3000	1000	2000	2000	18000	0	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	73	1	16	1	1	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	85	25	3000	1000	2000	2000	18000	0	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	73	1	16	1	1	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	43	25	3000	1000	2000	2000	18000	1	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	73	1	16	1	1	538	1000	1000	1000	542	542	542	542	542
2004	541	5	30	43	25	3000	1000	2000	2000	18000	0	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	73	1	16	1	1	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	43	25	3000	1000	2000	2000	18000	0	522	541	541	248	3	274	2000	2000	2000	541	623	1	1	1001	1000	0	0	73	1	16	1	1	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	43	25	3000	1000	2000	2000	18000	0	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	73	1	16	1	1	538	1000	1000	1000	542	542	542	542	542
2004	541	4	6	43	25	3000	1000	2000	2000	18000	0	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	73	1	16	1	1	538	1000	1000	1000	542	542	542	542	542
2004	541	4	18	43	25	3000	1000	2000	2000	18000	0	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	73	1	16	1	1	538	1000	1000	1000	542	542	542	542	542

Test 2: Latency 1->2 roundtrip

Code:

  fcvtpu x0, d0
  fmov d0, x0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 13.0038

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30204	130040	974	0	0	0	0	0	0	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	0	130013	0	130038	130038	125483	6	126242	30100	200	10002	20006	200	10002	20006	130038	130038	1	1	20201	100	99	100	10100	10000	100	10000	0	0	0	1	1	1	1317	0	1	16	1	1	129534	10000	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	974	0	0	0	0	0	0	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	0	130013	0	130038	130038	125483	6	126242	30100	200	10002	20006	200	10002	20006	130038	130038	1	1	20201	100	99	100	10100	10000	100	10000	0	0	0	1	1	1	1317	0	1	16	1	2	129533	10000	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	974	0	0	0	0	0	0	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	0	130013	0	130038	130038	125476	3	126246	30100	200	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	10000	0	0	0	0	0	0	1310	1	2	16	3	3	129525	10000	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	974	0	0	0	0	0	0	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	0	130013	0	130038	130038	125476	3	126246	30100	200	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	10000	0	0	0	0	1	0	1310	1	2	16	3	3	129525	10000	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	974	0	0	0	0	0	0	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	0	130013	0	130038	130038	125476	3	126246	30100	200	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	10000	0	0	0	0	0	0	1385	1	2	16	2	2	129525	10000	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	974	0	0	0	0	0	0	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	0	130013	0	130038	130038	125476	3	126246	30100	200	10000	20000	200	10000	20000	130073	130058	1	1	20201	100	99	100	10100	10000	100	10000	0	0	0	0	0	0	1310	1	2	16	2	2	129569	10000	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	974	0	0	0	0	0	0	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	0	130013	0	130038	130038	125476	3	126246	30100	200	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	10000	0	0	0	0	0	0	1310	1	2	16	3	2	129525	10000	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	974	0	0	0	0	96	0	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	0	130013	0	130074	130038	125512	3	126246	30100	200	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	10000	0	0	0	0	0	0	1310	1	3	16	2	3	129525	10000	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	975	0	0	0	0	0	0	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	0	130013	0	130038	130038	125476	3	126246	30100	200	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	10000	0	0	0	0	0	0	1310	1	2	16	2	3	129525	10000	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	974	0	0	0	0	0	0	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	0	130013	0	130038	130038	125476	3	126246	30100	200	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	10000	0	0	0	1	0	0	1389	1	1	16	2	3	129527	10007	10000	10000	10100	130039	130039	130039	130039	130039

1000 unrolls and 10 iterations

Result (median cycles for code): 13.0038

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	18	19	1e	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	5f	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cf	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	ec	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30024	130038	974	0	0	0	24	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	0	0	130013	0	130038	130038	125498	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	0	0	0	1270	0	0	2	16	1	1	129525	10000	16	0	10000	10000	10010	130039	130039	130039	130039	130039
30024	130038	974	0	0	0	0	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	0	0	130013	0	130038	130038	125498	3	126271	30010	20	10000	20000	20	10000	20000	130038	130040	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	0	0	0	1270	0	0	1	16	1	1	129525	10000	0	0	10000	10000	10010	130039	130039	130043	130039	130039
30024	130038	973	0	0	0	0	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	0	0	130013	0	130038	130038	125498	3	126268	30010	20	10066	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	0	0	0	1270	0	0	1	16	1	1	129525	10000	0	0	10000	10000	10010	130039	130039	130039	130039	130039
30024	130038	974	0	0	0	0	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	1	1	130013	0	130038	130038	125498	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	0	0	0	1270	0	0	1	16	1	1	129525	10000	0	0	10000	10000	10010	130039	130039	130039	130039	130039
30024	130039	974	0	0	0	0	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	0	1	130013	0	130038	130041	125498	3	126268	30010	20	10000	20000	20	10000	20000	130043	130049	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	0	0	0	1270	0	0	1	16	1	1	129525	10000	0	0	10000	10000	10010	130039	130039	130039	130039	130039
30024	130038	974	0	0	0	0	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	0	1	130013	0	130038	130038	125498	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	0	10000	1	0	6	0	0	0	1270	0	0	1	16	1	1	129525	10000	0	0	10000	10000	10010	130039	130039	130039	130043	130039
30024	130038	974	0	0	0	96	130023	119417	25	40010	10014	20000	10000	10	20000	10000	50	6214979	14800025	0	1	130013	0	130038	130038	125498	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	0	0	0	1270	0	0	1	16	1	1	129525	10000	0	0	10000	10000	10010	130039	130039	130039	130039	130039
30024	130038	974	0	0	0	0	130023	119422	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	0	0	130013	0	130038	130039	125498	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	0	10000	1	0	0	0	0	0	1270	0	0	1	16	1	1	129525	10000	0	0	10000	10000	10010	130069	130039	130039	130039	130039
30024	130038	974	0	0	0	0	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	0	0	130013	0	130038	130038	125498	3	126268	30010	20	10000	20000	20	10000	20000	130038	130117	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	24	0	1	0	1270	0	0	1	16	1	1	129525	10000	0	0	10000	10000	10010	130039	130039	130039	130039	130039
30024	130038	974	0	0	0	9	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	0	1	130013	0	130038	130038	125498	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	0	0	0	0	1270	0	0	2	16	1	1	129525	10000	0	0	10000	10000	10010	130039	130124	130039	130039	130122

Test 3: throughput

Count: 8

Code:

  fcvtpu x0, d8
  fcvtpu x1, d8
  fcvtpu x2, d8
  fcvtpu x3, d8
  fcvtpu x4, d8
  fcvtpu x5, d8
  fcvtpu x6, d8
  fcvtpu x7, d8

Initialization

  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	40066	300	0	0	0	0	32	25	240104	80100	160004	100	160020	500	1440132	40022	40041	40041	19977	6	19992	160120	200	160032	200	160032	40041	40123	1	1	80201	100	99	100	80100	100	0	0	0	0	1	1	1	5117	0	16	0	0	40038	80000	80000	80100	40042	40042	40042	40042	40042
160204	40041	300	0	0	0	0	32	25	240104	80100	160004	100	160236	500	1440132	40022	40041	40041	19977	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	0	0	1	1	1	5117	0	16	0	0	40038	80000	80000	80100	40042	40042	40042	40042	40042
160204	40041	300	0	0	0	0	32	25	240104	80100	160004	100	160020	500	1440132	40022	40041	40041	19977	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	0	0	1	1	1	5117	0	16	0	0	40038	80000	80000	80100	40042	40042	40042	40042	40042
160204	40041	300	0	0	0	0	32	25	240104	80100	160004	100	160020	500	1440132	40022	40041	40041	19977	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	0	0	1	1	1	5117	0	16	0	0	40038	80000	80000	80100	40042	40042	40042	40042	40042
160204	40041	300	0	0	9	0	74	25	240104	80100	160004	100	160020	500	1440132	40022	40041	40041	19977	6	19992	160120	202	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	0	0	1	1	1	5117	0	16	0	0	40038	80000	80000	80100	40042	40042	40042	40042	40042
160204	40041	299	0	0	0	0	32	25	240104	80100	160004	100	160020	500	1440132	40022	40041	40124	19977	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	0	3	1	1	1	5117	0	16	0	0	40038	80000	80000	80100	40042	40042	40042	40042	40042
160204	40041	300	0	0	0	0	32	25	240104	80100	160004	100	160020	500	1440132	40022	40041	40041	19977	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	0	0	1	1	1	5117	1	16	0	0	40038	80000	80000	80100	40042	40042	40042	40042	40042
160204	40041	300	0	0	0	0	32	25	240104	80100	160004	100	160200	500	1440132	40022	40041	40041	20002	14	20080	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	0	3	1	1	1	5117	0	16	0	0	40038	80000	80000	80100	40042	40042	40042	40042	40042
160204	40041	299	0	0	0	0	32	25	240104	80100	160004	100	160020	500	1440132	40022	40041	40041	19977	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	0	0	1	1	1	5117	0	16	0	0	40038	80000	80000	80100	40042	40042	40042	40042	40042
160204	40041	300	0	0	0	0	32	25	240104	80100	160004	100	160020	500	1440132	40022	40041	40041	19977	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	0	0	1	1	1	5117	0	16	0	0	40038	80000	80000	80100	40042	40042	40042	40042	40042

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	1e	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	c2	cf	d0	d2	d5	map dispatch bubble (d6)	db	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	40042	300	0	0	0	0	0	12	0	943	25	240010	80010	160000	10	160000	50	1440000	0	0	0	40022	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	2	1	3	0	5020	5	3	4	16	0	4	3	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	300	0	0	0	0	0	12	0	238	25	240010	80010	160000	10	160000	50	1440000	0	0	0	40022	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	5020	5	0	4	16	0	3	4	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	300	0	0	0	0	0	0	0	42	25	240010	80010	160000	10	160000	50	1447096	0	1	5	40022	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	5	3	0	0	5020	5	4	8	16	0	4	3	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	299	0	0	0	0	0	0	0	42	25	240010	80010	160000	10	160000	50	1447366	0	0	0	40022	40041	40041	19996	3	20021	160814	20	160000	20	160000	40041	40041	5	1	80021	10	9	10	80010	10	0	0	0	0	0	0	5020	0	0	4	16	0	7	6	40300	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	300	0	0	0	0	0	0	0	42	25	240010	80010	160000	10	160000	50	1440000	0	0	0	40022	40041	40041	19996	26	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	5020	0	0	5	16	0	3	4	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	300	0	0	0	0	0	0	0	612	25	240010	80010	160000	10	160000	50	1440000	0	1	5	40022	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	5020	0	0	3	16	0	3	4	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	299	0	0	0	0	0	15	0	42	25	240010	80010	160000	10	160000	50	1440000	0	0	0	40022	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	5020	0	0	6	16	0	4	3	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	300	0	0	0	0	0	0	0	707	25	240010	80010	160000	10	160000	50	1440000	0	0	0	40022	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	5020	0	0	6	16	0	6	7	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	300	0	0	0	0	0	0	0	42	25	240010	80010	160196	10	160000	50	1440000	0	1	0	40022	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	5020	0	0	6	16	0	6	4	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	300	0	0	0	0	0	0	0	42	25	240010	80010	160000	10	160000	50	1440000	0	0	0	40022	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	0	1	3	0	5020	0	0	4	16	0	6	4	40038	80000	80000	80010	40042	40042	40042	40042	40042

FCVTPU (scalar, D to X)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations