Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FCVTPU (scalar, H to H)

Test 1: uops

Code:

  fcvtpu h0, h0
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03181e1f3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004303724000822547251000100010003981603018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
10043037231088612547251000100010003981603018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
1004303723000612547251000100010003981603018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
1004303723000612547251000100010003981603018303730372414328951000100010003037303711100110001073116112629100030383038303830383038
1004303723000612547251000100010003981603018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
1004303724000612547251000100010003981603018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
1004303724000612547251000100010003981603018303730372414328951000100010003037303711100110000073116122629100030383038303830383038
1004303723000612547251000100010003981603018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
10043037230003712547251000100010003981603018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
1004303723000612547251000100010003981603018303730372414328951000100010003037303711100110000073116112629100030383038303830383038

Test 2: Latency 1->2

Code:

  fcvtpu h0, h0
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fst unit uop (a7)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0ea? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020430037233006129547251010010010000100100005004277160130018300373003728264328745101002001000020010000300373003711102011009910010010000100000071011611296330100001003003830038300383003830038
1020430037232006129547251010010010000100100005004277160130018300373003728264328745101002001000020010000300373003711102011009910010010000100000071011611296330100001003003830038300383003830038
1020430037232096129547251010010010000100100005004277160130018300373003728264328745101002001018220010000300373003711102011009910010010000100000071011611296330100001003003830038300383003830038
1020430037232006129547251010010010000100100005004277160130018300373003728264328745101002001000020010000300373003711102011009910010010000100000071011611296330100001003003830038300383003830038
1020430037233006129547251010010010000100100005004277160130018300373003728264328745101002001000020010000300373003711102011009910010010000100100071013211296330100001003003830038300383003830038
1020430037233106129547251010010010000100100005004277160130018300373003728264328745101002001000020010000300373003711102011009910010010000100002071011611296330100001003003830038300383003830038
1020430037233006129547251010010010000100100005004277160130018300373003728264328745101002001000020010000300373003711102011009910010010000100000071011611296330100001003003830038300383003830038
1020430037233006129547251010010010000100100005004277160130018300373003728264328745101002001000020010000300373003711102011009910010010000100000071011611296330100001003003830038300383003830038
1020430037233006129547251010010010000100100005004277160130018300373003728264328745101002001000020010000300373003711102011009910010010000100000071011611296330100001003003830038300383003830038
102043003723300151729547251010010010000100100005004277160030018300373003728264328745101002001000020010000300373003711102011009910010010000100010071021611296330100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024300372250000006129547251001010100001010000504277160030018300373003728286328767100102010000201000030037300371110021109101010000100000000006402162229629010000103003830038300383003830038
10024300372260000006129547251001010100001010000504277160030018300373003728286328767100102010000201000030037300371110021109101010000100000000006402162229629010000103003830038300383003830038
10024300372240000006129547251001010100001010000504277160130018300373003728286328767100102010000201000030037300371110021109101010000100000000006402162229629010000103003830038300383003830038
10024300372250000006129547251001010100001010000504277160130018300373003728286328767100102010000201000030037300371110021109101010000100000000006402162229629010000103003830038300383003830038
10024300372250000006129538441001010100001010000504277160030018300373003728286328767100102010000201000030037300371110021109101010000100000000006402162229629010000103003830038300383003830038
10024300372250000006129547251001010100001010000504277160030018300373003728286328767100102010000201000030037300371110021109101010000100000000006402162229629010000103003830038300383003830038
10024300372250000006129547251001010100001010000504277160030018300373003728286328767100102010000201000030037300371110021109101010000100000000006402162229629010000103003830038300383003830038
10024300372250000006129547251001010100001010000504277160030018300373003728286328767100102010000201000030037300371110021109101010000100000000006403162229629010000103003830038300383003830038
10024300372250000006129529251001010100001010000504277160030018300373003728286328767100102010000201000030037300371110021109101010000100000000006402162229629010000103003830038300383003830038
100243003722500000012429547251001010100001010000504277160030018300373003728286328767100102010000201000030037300371110021109101010000100000000106403162229629010000103003830038300383003830038

Test 3: throughput

Count: 8

Code:

  fcvtpu h0, h8
  fcvtpu h1, h8
  fcvtpu h2, h8
  fcvtpu h3, h8
  fcvtpu h4, h8
  fcvtpu h5, h8
  fcvtpu h6, h8
  fcvtpu h7, h8
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420039161000000030258010810080109100800205006401320200200200392003999776999080120200800322008003220039200391180201100991001008000010000000111511821645200360800001002004020040200402004020040
80204200391560000810072258010810080008100800205006401320200200200392003999776999080120200800322008003220039200391180201100991001008000010000000111511831623200360800001002004020040200402004020040
8020420039155000000030258010810080008100800205006401320200203200392003999776999080120200800322008003220039200391180201100991001008000010000000111511831643200360800001002004020040200402004020040
802042003915500004500030258010810080008100800205006401320200200200392003999776999080120200800322008003220039200391180201100991001008000010000000111511831643200360800001002004020040200402004020040
802042003915500002880030258010810080008100800205006401320200200200392003999776999080120200800322008003220039200391180201100991001008000010000000111511831633200360800001002004020040200402004020040
80204200391560000000529258010810080008100800205006401320200200200392003999776999080120200800322008003220039200391180201100991001008000010000000111511831633200360800001002004020040200402004020040
8020420039155000090030258010810080008100800205006401321200200200392003999776999080120200800322008003220039200391180201100991001008000010000000111511831632200360800001002004020040200402004020040
8020420039155000000030258010810080008100800205006401320200200200392003999776999080120200800322008003220039200391180201100991001008000010000000111511821642200360800001002004020040200402004020040
80204200391560000390030258010810080008100800205006401321200200200392003999776999080120200800322008003220039200391180201100991001008000010000000111511831632200360800001002004020040200402004020040
80204200391550000270030258010810080008100800205006401320200200200392003999776999080120200800322008003220039200391180201100991001008000010000000111511831632200360800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)dbddfetch restart (de)e0eaeb? simd retires (ee)? int retires (ef)f5f6f7f8fd
800242005015609402580109108000010800005064000000200202003920039999631001980010208000020800002003920039118002110910108000010005038316044200360080000102004020040200912009120040
80024200391551144402580010108000010800005064000000200202003920039999631001980010208000020800002003920039118002110910108000010005020316044200360080000102004020040200402004020040
8002420039156004202580010108000010800005064000001200202003920039999631001980010208000020800002003920039118002110910108000010005020316153200360080000102004020040200402004020040
800242003915500402580010108000010800005064000010200202003920039999631001980010208000020800002003920039118002110910108000010035020316055200360080000102004020040200402004020040
800242003915600402580010108000010800005064000011200202003920039999631001980010208000020800002003920039118002110910108000010005020416044200360080000102004020040200402004020040
800242003915600402580010108000010800005064000000200202003920089999631001980010208000020800002003920039118002110910108000010005020416085200360080000102004020040200402004020040
800242003916100402580010108000010800005064000000200202003920039999631001980010208000020800002003920039118002110910108000010005020416054200360080000102004020040200402004020040
8002420039156001352580010108000010800005064000001200202003920039999631001980010208000020800002003920039118002110910108000010005020316044200360080000102004020040200402004020040
800242003915500402580010108000010800005064000000200202003920039999631001980010208000020800002003920039118002110910108000010005020416045200360080000102004020040200402004020040
800242003915500402580010108000010800005064000000200202003920039999631001980010208000020800002003920039118002110910108000010005020516034200360080000102004020040200402004020040