Apple M1 Microarchitecture Research by Dougall Johnson

Firestorm: Overview | Base Instructions | SIMD and FP Instructions
Icestorm:  Overview | Base Instructions | SIMD and FP Instructions

FCVTPU (scalar, H to W)

Test 1: uops

Code:

  fcvtpu w0, h0
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 3.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 2.000

retire (01)cycle (02)031e3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch fp/simd (57)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op fp/simd (7e)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst integer (97)a8accfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
2004541404325300010002000200018000152254154124832742000200020005415411110011000007311611538100010001000542542542542542
2004541504325300010002000200018000052254154124832742000200020005415411110011000007311611538100010001000542542542542542
2004541434325300010002000200018000052254154124832742000200020005415411110011000007311611538100010001000542542542542542
2004541404325300010002000200018000152254154124832742000200020005415411110011000007311611538100010001000542542542542542
2004541408525300010002000200018000052254154124832742000200020005415411110011000007311611538100010001000542542542542542
2004541404325300010002000200018000152254154124832742000200020005415411110011000007311611538100010001000542542542542542
2004541404325300010002000200018000052254154124832742000200020005415411110011000107311611538100010001000542542542542542
2004541404325300010002000200018000052254154124832742000200020005415411110011000007311611538100010001000542542542542542
2004541404325300010002000200018000052254154124832742000200020005415411110011000007311611538100010001000542542542542542
20045414124325300010002000200018000052254154124832742000200020005415411110011000007311611538100010001000542542542542542

Test 2: Latency 1->2 roundtrip

Code:

  fcvtpu w0, h0
  fmov d0, x0
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 13.0075

retire (01)cycle (02)0304080b18191e1f3a3f4f51inst issue (52)~issue int (53)~issue fp/simd (54)~issue ld/st (55)~dispatch int (56)~dispatch fp/simd (57)~dispatch ld/st (58)huge thing int (59)huge thing ld/st (5a)huge thing fp/simd (5b)60696b6d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op ld/st (7d)~map op fp/simd (7e)~map lookup int (7f)~map lookup ld/st (80)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa1a6a8accfd5d6ddinst fetch restart (de)e0? int output thing (e9)ld/st retires (ed)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
30204130136975000000021300231194172540100101002000010000100200001000050062149791480103401300130130038130038125476312624630100200100002000020010000200001300381300391120201100991001010010000100010000041413149168912952510000100001000010100130039130039130039130039130039
302041300389750000000213002311941725401001010020000100001002000010000500621497914801034113001301300381300381254763126246301002001000020000200100002000013003813003811202011009910010100100001000100000013148167812952510000100001000010100130039130039130039130039130039
302041300389740000000213002311941725401001010020012100061002000010000500621497914801034113001301300381300381254763126246301002001000020000200100002000013003813003811202011009910010100100001000100000013149167812952510000100001000010100130039130039130039130039130039
30204130038975000000021300231194172540100101002000010000100200001000050062151231480103401300133130038130038125476312624630100200100002000020010000200001300381300381120201100991001010010000100010000025213148167812952510000100001000010100130039130039130039130039130041
302041301059760002000213002311941725401001010020000100001002000010000500621497914801034113001301300381300381254763126246301002001000020000200100002000013003813003811202011009910010100100001000100000013149167812952510000100001000010100130039130039130039130039130039
302041300389740000000213002311941725401001010020000100001002000010000500621512314801034113001301300381300381254763126246301002001000020000200100002000013003813011211202011009910010100100001000100000013145168812952510000100001000010100130039130039130039130039130039
302041300389750000000213002311941725401001010020000100001002000010000500621497914801034113001301300381300381254763126246301002001000020000200100002000013003813003811202011009910010100100001000100000013149167912952510000100001000010100130039130039130039130039130039
302041300389750000000213002311941725401001010020000100001002000010000500621497914801034113001301300381300381254763126246301002001000020000200100002000013003813003811202011009910010100100001000100000013149167812952510000100001000010100130039130039130039130077130077
302041300829750000000213002311941725401001010020000100001002000010000500621507514801034013001301300381300381254763126246301002001000020000200100002000013003813003811202011009910010100100001000100000013148165612952510000100001000010100130039130039130039130039130039
302041300389751001000213002311941725401001010020000100001002000010000500621497914801034013001301300381300381254763126246301002001000020128200100002000013003813003811202011009910010100100001000100000013148167812952510000100001000010100130039130039130039130039130042

1000 unrolls and 10 iterations

Result (median cycles for code): 13.0038

retire (01)cycle (02)0308090b18191e1f3f4f51inst issue (52)~issue int (53)~issue fp/simd (54)~issue ld/st (55)~dispatch int (56)~dispatch fp/simd (57)~dispatch ld/st (58)huge thing int (59)huge thing ld/st (5a)huge thing fp/simd (5b)60696b6d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op ld/st (7d)~map op fp/simd (7e)~map lookup int (7f)~map lookup ld/st (80)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa6a8a9accficache miss (d3)d5d6ddinst fetch restart (de)e0? int output thing (e9)eald/st retires (ed)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
30024130038974000000013002311941725400101001320000100001020000100005062149791480002501300130130038130074125498312626830010201000020000201000020000130038130039112002110910100101000010100000001270011611129525100000100001000010010130039130039130039130039130039
3002413003897300000738013002311941725400101001020000100001020000100005062149791480002501300130130038130038125498312626830010201000020000201000020000130038130038112002110910100101000010100000001270011612129525100000100001000010010130039130039130039130039130039
30024130038974000000013002311941725400101001020000100051220000100005062149791480002501300130130038130038125498312626830010201000020000201000020000130074130038112002110910100101000010100000001270011611129525100000100001000010010130039130039130039130039130039
30024130038974000000013002311941725400101001020000100001020000100005062149791480002501300130130038130038125498312626830010201000020000201000020000130038130038112002110910100101000010100000001270021611129525100000100001000010010130039130039130039130039130039
30024130038974000000013002311941725400101001020000100001020000100005062149791480002501300130130048130038125498312626830010201000020000201000020000130038130038112002110910100101000010100000001270011611129525100000100001000010010130039130039130040130039130039
30024130038974000000013002311941725400101001020000100001020000100005062149791480002501300130130038130038125498312626830010201000020000201000020000130038130038112002110910100101000010100000001270011611129525100000100001000010010130039130039130039130039130039
30024130038974000000013002411941725400101001020000100001020000100005062149791480002501300130130038130038125498312626830010201000020000201000020000130038130040112002110910100101000010100000001270011611129525100000100001000010010130039130039130039130039130039
3002413003897400000579013002311941725400101001020000100021020000100005062149791480002511300130130038130038125498312626830010201000020000201000020000130041130038112002110910100101000010100001031270011611129525100000100001000010010130039130039130039130039130039
30024130038974000009013002311941725400101001020000100001020000100005062149791480002511300130130038130039125498312626830010201000020000201000020000130038130038112002110910100101000010100003001270011611129525100000100001000010010130044130162130041130039130039
30024130038974000000013002311941725400101001020000100001020000100005062149791480002501300130130038130038125498312626830010201000020000201000020000130038130038112002110910100101000010100000001270011622129525100000100001000010010130042130039130042130039130039

Test 3: throughput

Count: 8

Code:

  fcvtpu w0, h8
  fcvtpu w1, h8
  fcvtpu w2, h8
  fcvtpu w3, h8
  fcvtpu w4, h8
  fcvtpu w5, h8
  fcvtpu w6, h8
  fcvtpu w7, h8
  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

retire (01)cycle (02)0307080b18191e1f3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)9fa0a1a6a8a9acc2c5branch mispredict (cb)cdcfd5d6inst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
16020440062300000006303225240104801001600041001600205001440132040022400414004119977619992160120200160032200160032400414004111802011009910080100100000000011151170160400388000080000801004004240042400424004240042
1602044004130000000003225240104801001600041001600205001440132040022400414004119977619992160120200160032200160032400414004111802011009910080100100000000011151170160400388000080000801004004240042400424004240042
16020440041300000001803225240104801001600041001600205001440132040022400414004119977619992160120200160032200160032400414004111802011009910080100100000000011151170160400388000080000801004004240042400424004240042
1602044004130000010003225240104801001600041001600205001440132040022400414004119977619992160120200160032200160032400414004111802011009910080100100000000011151170160400388000080000801004004240042400424004240042
16020440041300000000069725240104801001600041001600205001440132040022400414004119977619992160120200160032200160032400414004111802011009910080100100000000011151170160400388000080000801004004240042400424004240042
1602044004130000000003225240104801001600041001600205001440132040022400414004119977619992160120200160032200160032400414004111802011009910080100100000000011151170160400388000080000801004004240042400424004240042
1602044004130000000003225240104801001600041001600205001440132040022400414004119977619992160120200160032200160032400414004111802011009910080100100000000011151170160400388000080000801004004240042400424004240042
1602044004130000000003225240104801001600041001600205001440132040022400414004119977619992160312200160032200160032400414004111802011009910080100100000000011151171160400388000080000801004004240042400424004240042
1602044004130000000003225240104801821600041001600205001440132040022400414004119977619992160120200160032200160032400414004111802011009910080100100000000011151170160400388000080000801004004240042400424004240042
16020440041299000002403225240104801001600041001600205001440132040022400414004119977619992160120200160032200160032400414004111802011009910080100100000000011151170160400388000080000801004004240042400424004240042

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

retire (01)cycle (02)0308191e3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)5f60696b6d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)9fa0a6a7a8acc2branch mispredict (cb)cdcfd0icache miss (d3)d5d6ddinst fetch restart (de)e0? int output thing (e9)ea? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
160024400423000004225240010800101600001016000050144000000400220400414004119996320021160010201600002016000040041400411180021109108001010000000005020061116644003880000080000800104004240042400424004240042
16002440041300000422524001080010160000101600005014400000140022040041400411999632002116001020160000201600004004140041118002110910800101000000000502005416464003880000080000800104004240042400424004240042
16002440041299000422524001080010160000101600005014400000140068340041400411999632002116001020160000201600004004140041118002110910800101000000000502005616664003880000080000800104012440042400424004240042
16002440041300000422524001080010160000101600005014400000040022040041400411999632002116001020160000201600004004140041118002110910800101000000000502004716564003880000080000800104004240042400424004240042
160024400413000004225240010800101600001016000050144186200400220400414004119996320021160010201600002016000040041400411180021109108001010000450000502005616464003880000080000800104004240042400424004240042
16002440041299000422524001080010160000101600005014400000040022040041400411999632002116001020160000201600004004140041118002110910800101000000000502005616754003880000080000800104004240042400424004240042
16002440041300000842524001080010160000101600005014400000040022040041400411999632002116001020160000201600004004140041118002110910800101000000010502005616554003880000080000800104004240042400424004240042
16002440041300000422524001080010160000101600005014400000040022040041400411999632002116001020160000201600004004140041118002110910800101000000000502005616764003880000080000800104004240042400424004240042
16002440041299000422524001080010160000101600005014400000040022040041400411999632002116001020160000201600004004140041118002110910800101000000000502004616644003880000080000800104004240042400424004240099
16002440041300000422524001080010160000101600005014400000040022040041400411999632002116001020160000201600004004140041118002110910800101000000000502004416664003880000080000800104004240042400424004240042