Apple M1 Microarchitecture Research by Dougall Johnson

Firestorm: Overview | Base Instructions | SIMD and FP Instructions
Icestorm:  Overview | Base Instructions | SIMD and FP Instructions

FCVTPU (scalar, H to X)

Test 1: uops

Code:

  fcvtpu x0, h0
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 3.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 2.000

retire (01)cycle (02)031e3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch fp/simd (57)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op fp/simd (7e)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst integer (97)a8cfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
2004541403032530001000200020001800015225415412483274200020002000541541111001100007311611538100010001000542542542542542
200454140432530001000200020001800005225415412483274200020002000541541111001100007311611538100010001000542542542542542
200454140432530001000200020001800005225415412483274200020002000541541111001100007311611538100010001000542542542542542
200454150432530001000200020001800005225415412483274200020002000541541111001100007311611538100010001000542542542542542
200454140432530001000200020001800005225415412483274200020002000541541111001100007311611538100010001000542542542542542
200454140432530001000200020001800015225415412483274200020002000541541111001100007311611538100010001000542542542542542
200454140512530001000200020001800005225415412483274200020002000541541111001100017311611538100010001000542542542542542
200454140432530001000200020001800005225415412483274200020002000541541111001100007311611538100010001000542542542542542
200454140432530001000200020001800015225415412483274200020002000541541111001100007311611538100010001000542542542542542
200454150432530001000200020001800005225415412483274200020002000541541111001100007311611538100010001000542542542542542

Test 2: Latency 1->2 roundtrip

Code:

  fcvtpu x0, h0
  fmov d0, x0
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 13.0038

retire (01)cycle (02)0308090b18191e1f3f4f51inst issue (52)~issue int (53)~issue fp/simd (54)~issue ld/st (55)~dispatch int (56)~dispatch fp/simd (57)~dispatch ld/st (58)huge thing int (59)huge thing ld/st (5a)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op ld/st (7d)~map op fp/simd (7e)~map lookup int (7f)~map lookup ld/st (80)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa1a6a8a9acc2c5branch mispredict (cb)cdcfd0d5d6ddinst fetch restart (de)e0? int output thing (e9)ld/st retires (ed)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
3020413003897400000001300231194172540100101002000010000100200001000050062149791480103411300911300381300381254763126246301002001000020000200100002000013003813003811202011009910010100100001000100000000000131012162212952510000100001000010100130039130039130039130039130039
3020413003897400000001300231194172540100101002000010000100200001000050062149791480103411300131300381300381254763126251301002001000020000200100002000013003813003811202011009910010100100001000100000000000131012162212952510000100001000010100130039130039130039130039130039
3020413003897400000601300231194172540100101002000010000100200001000050062149791480103411300521300591300391254763126246301002001000020000200100002000013003813003811202011009910010100100001000100000000000131012162212952510000100001000010100130039130039130039130039130039
3020413003897400000001300231194172540100101002000010000100200001000050062149791480103411300531300381300381254763126246301002001000020000200100002000013003813007011202011009910010100100001000100000000000131012162212952510000100001000010100130039130039130039130039130039
3020413003897400000001300231194172540100101002000010000100200001000050062149791480103411300131300411300381254763126246301002001000020000200100002000013003813003811202011009910010100100001000100000000000131012162212952510000100001000010100130039130039130039130039130039
3020413003897400000001300231194172540100101002000010000116200001000050062149791480103411300751300381300381254763126246301002001000020000200100002000013003813003811202011009910010100100001000100000030000131012162212952510000100001000010100130039130039130039130039130039
3020413003897400000001300561194172540100101002000010000100200001000050062149791480103411300141302081300411254763126446301002001000020000200100002000013004013003811202011009910010100100001000100000000000131012162212952510000100001000010100130039130043130039130039130039
302041300389740000057881300231194172540100101002000010000103201161000051062266531480103411300641301181300381254773126246302742001000020244202100002012213003813003911202011009910010100100001000100000030000131012162212952710000100001000010100130039130039130039130039130039
3020413003897400000001300231194172540100101002000010000100200001000050062150271480149011300131300381300381254763126246301002001000020000200100002000013003813003811202011009910010100100001000100000000000131014162212952510000100001000010100130042130039130041130042130039
3020413003897400000001300231194172540100101002000010000100200001000050062149791480103411300621300381300381254763126246301002001000020000200100002000013003813003811202011009910010100100001000100000000000131012162212952510000100001000010100130039130039130039130039130039

1000 unrolls and 10 iterations

Result (median cycles for code): 13.0038

retire (01)cycle (02)0307080a18191e1f3a3f4f51inst issue (52)~issue int (53)~issue fp/simd (54)~issue ld/st (55)~dispatch int (56)~dispatch fp/simd (57)~dispatch ld/st (58)huge thing int (59)huge thing ld/st (5a)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op ld/st (7d)~map op fp/simd (7e)~map lookup int (7f)~map lookup ld/st (80)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa6a8accdcfd5d6ddinst fetch restart (de)e0? int output thing (e9)ld/st retires (ed)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
300241300389741010000213002311941725400101001020000100001020000100005062149791480002511300131300381300381254983126268300102010000200002010000200001300381300381120021109101001010000101000000012741616121612952510000100001000010010130039130039130039130039130039
300241300389741010000213002311941725400101001020000100001020000100005062149791480002501300131300381300381254983126268300102010000200002010000200001300381300381120021109101001010000101000000012741416131512952510000100001000010010130039130039130039130039130039
300241300389741010000213002311941725400101001020000100001020000100005062149791480002501300131300381300381255153126268300102010000200002010000200001300381301361120021109101001010000101000000012741516141312952510000100001000010010130039130039130039130039130039
300241300389741010000213005911941725400101001020000100001020000100005562149791480002501300131300381300381254983126268300102010000201312010000200001300381300431120021109101001010000101000000012741516131612952510000100001000010010130039130039130039130039130039
300241300389741010000213002311941725400101001020000100001020000100005062149791480002501300131300381300381254983126268300102010000200002010000200001300381300381120021109101001010000101000000012741516141712952510000100001000010010130039130039130039130039130039
300241300389741010000213002311941725400101001020000100001020000100005062149791480002501300131300381300381254983126268300102010000200002010000200001300381300381120021109101001010000101000000012741516141512952510000100001000010010130039130039130039130039130039
300241300389741010000213002311941725400101001020000100001020000100005062149791480002501300131300381300381254983126268300102010000200002010000200001300381300381120021109101001010000101000000012741516131612952510000100001000010010130039130039130039130039130039
3002413003997410100002130023119417254001010010200001000010200001000050621497914800025013001313003813003812549831262683001020100002000020100002000013003813003811200211091010010100001010000601211274151614912952510000100001000010010130039130039130039130039130039
300241300389741010000213002311941725400101001020000100001020000100005062149791480002501300131300401300381254983126268300102010000200002010000200001300381300381120021109101001010000101000000012741416131412952510000100001000010010130039130039130043130039130039
300241300389741010000213002311941725400161001020000100001020000100005062149791480002501300131300381300381254983126268300102010000200002010000200001300381300381120021109101001010000101000000012741716121412957410000100001000010010130039130039130039130039130039

Test 3: throughput

Count: 8

Code:

  fcvtpu x0, h8
  fcvtpu x1, h8
  fcvtpu x2, h8
  fcvtpu x3, h8
  fcvtpu x4, h8
  fcvtpu x5, h8
  fcvtpu x6, h8
  fcvtpu x7, h8
  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

retire (01)cycle (02)03080b18191e1f3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696d6edispatch stall (70)74scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)9fa1a8acc5branch mispredict (cb)cdcfd0d5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
160204400663100000007202524010480186160004100160020500144013204002240041400411997706199921601202001600322001600324004140041118020110099100801001000001115117011600400388000080000801004004240042400424004240042
16020440041310000000322524010480100160004100160020500144013214002240041400411997706199921601202001600322001600324004140041118020110099100801001000001115117001600400388000080000801004004240042400424004240042
16020440041311000000322524010480100160004100160020500144013214002240041400411997706199921601202001600322001600324004140041118020110099100801001000001115117001600400388000080000801004004240042400424004240042
16020440041311000000322524010480100160004100160020500144013214002240041400411997706199921601202001600322001600324004140041118020110099100801001000001115117001600400388000080000801004004240042400424004240042
16020440041311000000322524010480100160004100160212500144013204002240125400411997706199921601202001600322001600324004140041118020110099100801001000101115117001600400388000080000801004004240042400424004240042
16020440041310000000322524010480100160004100160020500144013214002240041400411997706199921601202001600322001600324004140041118020110099100801001000001115117001600400388000080000801004004240042400424004240042
1602044004131000004890322524010480100160004100160020500144013214002240041400411997706199921601202001600322001600324004140041118020110099100801001000001115117001600400388000080000801004004240042400424004240042
16020440041310000000322524010480100160004100160020500144013214002240041400411997756199921601202001600322001600324004140041118020110099100801001000001115117001600400388000080000801004004240042400424004240042
16020440041310000000322524010480100160004100160020500144013214002240041400411997706200491601202001600322001600324004140041118020110099100801001000001115117001600400388000080000801004004240042400424004240042
16020440041310000000322524010480190160004100160020500144013204002240041400411997706199921601202001600322001600324004140041118020110099100801001000101115117001600400388000080000801004004240042400424004240042

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

retire (01)cycle (02)0308191e3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)5f60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)9fa8accfd5d6d9daddinst fetch restart (de)e0? int output thing (e9)ea? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
1600244005431000042252400108001016000010160000501440000014002240041400411999632002116001020160000201600004004140041118002110910800101000502051600254003880000080000800104004240042400424004240042
16002440041310000149252400108001016000010160000501440000014002240041400411999632002116001020160000201600004004140041118002110910800101000502021600244003880000080000800104004240042400424004240042
1600244004131100042252400108001016000010160000501440000014002240041400411999632002116001020160000201600004004140041118002110910800101000502041600364003880000080000800104004240042400424004240042
1600244004132200042252400108001016000010160000501440000014002240041400411999632002116001020160000201600004004140041118002110910800101000502041600424003880000080000800104004240042400424004240042
1600244004131000042252400108001016000010160000501440000004002240041400411999632002116042620160000201600004004140041118002110910800101000502021600444003880000080000800104004240042400424004240042
1600244004131000042252400108001016000010160000501440000004002240041400411999632002116001020160000201600004019840041118002110910800101000502021600244003880000080000800104004240042400424004240042
16002440041310000191252400108001016000010160000501440000014002240041400411999632002116001020160000201600004004140041118002110910800101000502021600244003880000080000800104004240042400424004240042
1600244004131000042252400108001016000010160000501440000014002240041400411999632002116001020160000201600004004140041118002110910800101000502041600424003880000080000800104004240042400424004240042
1600244004131100042252400108001016000010160000501440000014002240041400411999632002116001020160000201600004004140041118002110910800101000502041600434003880000080000800104004240042400424004240042
1600244004131100042252400108001016000010160000501440000014002240041400411999632002116001020160000201600004004140041118002110910800101000502041600644003880000080000800104004240042400424004240042