Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FCVTPU (scalar, S to S)

Test 1: uops

Code:

  fcvtpu s0, s0
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03191e1f3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10043037230006125472510001000100039816013018303730372414328951000100010003037303711100110000373116112629100030383038303830383038
10043037240006125472510001000100039816013018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
10043037230006125472510001000100039816013018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
10043037240006125472510001000100039816013018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
100430372311328810325472510001000100039816013018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
100430372300010325472510001000100039816013018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
10043037230006125472510001000100039816013018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
10043037230006125472510001000100039816013018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
10043037240006125472510001000100039816013018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
10043037240006125472510001000100039816013018303730372414328951000100010003037303711100110001073116112629100030383038303830383038

Test 2: Latency 1->2

Code:

  fcvtpu s0, s0
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03l2 tlb miss instruction (0a)1e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)accdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043003722505161295472510100100100001001000050042771601300183003730037282640328745101002001000020010000300373003711102011009910010010000100000007102162229633100001003003830038300383003830038
102043003722501561295472510100100100001001000050042771601300183003730037282640328745101002001000020010000300373003711102011009910010010000100000017102162229633100001003003830038300383003830038
10204300372250252119295472510100100100001001000050042771601300183003730037282647328745101002001000020410000300373003711102011009910010010000100002007102162229633100001003003830038300383003830038
10204300372250061295382510100100100001001000050042771601300183003730037282640328745101002001000020010000300373003711102011009910010010000100000007102162229633100001003003830038300383003830038
10204300372260061295472510100100100001001000050042771601300183003730037282640328745101002001000020010000300373003711102011009910010010000100000007102162229633100001003003830038300383003830038
10204300372250061295472510100100100001001000050042771600300183003730037282640328745101002001000020010000300373003711102011009910010010000100000007102162229633100001003003830038300383003830038
10204300372250961295472510100100100001001000050042771600300183003730037282640328745101002001000020010000300373003711102011009910010010000100000007102162229633100001003003830038300383003830038
1020430037225045061295472510100100100001001000050042771601300183003730037282640328745101002001000020010000300373003711102011009910010010000100001007102162229633100001003003830038300383003830038
1020430037225028561295472510100100100001001000050042771601300183003730037282640328745101002001000020010000300373003711102011009910010010000100000007102162229633100001003003830038300383008530038
102043003722403061295472510100100100001001000050042771600300183003730037282640328745101002001000020010000300373003711102011009910010010000100000007102162229633100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acc2branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
100243003722500000061295472510010101000010100005042771600300183003730037282863287671001020100002010000300373003711100211091010100001000006403163329629010000103003830038300383003830038
100243003722500000061295472510010101000010100005042771600300183003730037282863287671001020100002010000300373003711100211091010100001000006403163329629010000103003830038300383003830038
100243003722500000061295472510010101000010100005042771600300183003730037282863287671001020100002010000300373003711100211091010100001000006403163329629010000103003830038300383008630038
100243003722500000061295472510010101000010100005042771600300183003730037282863287671001020100002010000300373003711100211091010100001000006403163329629010000103003830038300383003830038
100243003722500000061295472510010101000010100005042771600300183003730037282863287671001020100002010000300373003711100211091010100001000006403163329629010000103003830038300383003830038
100243008422500000061295472510010101000010100005042771600300183003730037282863287671001020100002010000300373003711100211091010100001000006403163329629010000103003830038300383003830038
100243003722500000061295472510010101000010100005042771600300183003730037282863287671001020100002010000300373003711100211091010100001000006403163329629010000103003830038300383003830038
100243003722500000061295472510010101000010100005042771600300183003730037282863287671001020100002010000300373003711100211091010100001000016403163329629010000103003830038300383003830038
100243003722500000061295472510010101000010100005042771600300183003730037282863287671001020100002010000300373003711100211091010100001000006403163329629010000103003830038300383003830038
100243003722500000061295472510010101000010100005042771600300183003730037282863287671001020100002010000300373003711100211091010100001000006403163329629010000103003830038300383003830038

Test 3: throughput

Count: 8

Code:

  fcvtpu s0, s8
  fcvtpu s1, s8
  fcvtpu s2, s8
  fcvtpu s3, s8
  fcvtpu s4, s8
  fcvtpu s5, s8
  fcvtpu s6, s8
  fcvtpu s7, s8
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)l1d cache writeback (a8)a9acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80204200491500302580108100800081008002050064013202002020039200399977699908012020080032200800322003920039118020110099100100800001000000011151180160020036800001002004020040200402004020040
8020420039150020352580108100800081008002050064013202002020039200399977699908012020080032200800322003920039118020110099100100800001000000011151180160020036800001002004020040200402004020040
80204200391500302580108100800081008002050064013202002020039200399977699908012020080032200800322003920039118020110099100100800001000000011151180160020036800001002004020040200402004020040
80204200391500302580108100800081008002050064013202002020039200399977699908012020080032200800322003920039118020110099100100800001000000011151180160020036800001002004020040200402004020040
802042003915001562580108100800081008002050064013202002020039200399977699908012020080032200800322003920039118020110099100100800001000000011151180160020036800001002004020040200402004020040
802042003915002012580108100800081008002050064013202002020039200399977699908012020080032200800322003920039118020110099100100800001000000011151180160120036800001002004020040200402004020040
80204200391500932580108100800081008002050064013202002020039200399977699908012020080032200800322003920039118020110099100100800001000000011151180160020036800001002004020040200402004020040
80204200391500302580108100800081008002050064013202002020039200399977699908012020080032200800322003920039118020110099100100800001000000011151180160020036800001002004020040200402004020040
80204200391500302580108100800081008002050064013202002020039200399977699908012020080032200800322003920039118020110099100100800001000000011151180160020036800001002004020040200402004020040
80204200391780302580108100800081008002050064013202002020039200399977699908012020080032200800322003920039118020110099100100800001000000311151180160020036800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3f5051schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200511500040025800101080000108009950640000612002020039200399996310019800102080000208000020039200391180021109101080000100050201216472003680000102004020040200402004020040
80024200391500040200232580010108000010800005064000051200202003920039999631001980010208000020800002003920039118002110910108000010005020616652003680000102004020040200402004020040
80024200391610040025800101080000108000050640000512002020039200399996310019800102080000208000020039200391180021109101080000100050209161042003680000102004020040200402004020040
800242003915000705025800101080000108000050640000012002020039200399996310019800102080000208000020039200391180021109101080000100050204161242003680000102004020040200402004020040
80024200391500040025800101080000108000050640000002002020039200399996310019800102080000208000020039200391180021109101080000100050205164142003680000102004020040200402004020040
800242003915000400258001010800001080000506400000120020200392003999963100198001020800002080000200392003911800211091010800001000502013161252003680000102004020040200402004020040
8002420039156004002580010108000010800005064000001200202003920039999631001980126208000020800002003920039118002110910108000010005020516882003680000102004020040200402004020040
8002420039150004002580010108000010800005064000001200202003920039999631001980010208000020800002003920039118002110910108000010005020616482003680000102004020040200402004020040
8002420039150004002580010108000010800005064000001200202003920039999631001980010208000020800002003920039118002110910108000010005020131613132003680000102004020091200402004020040
80024200391500040025800101080000108000050640000002002020039200399996310019800102080000208000020039200391180021109101080000100050201316482003680000102004020040200402004020040