Firestorm: FCVTPU (scalar, S to W) measurements

Code:

  fcvtpu w0, s0

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 3.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 2.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
2004	541	4	0	0	0	0	43	25	3000	1000	2000	2000	18000	0	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	0	0	0	73	1	16	1	1	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	0	0	0	43	25	3000	1000	2000	2000	18000	0	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	0	0	0	73	1	16	1	1	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	0	0	0	43	25	3000	1000	2000	2000	18000	0	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	0	0	0	73	1	16	1	1	538	1000	1000	1000	542	542	542	542	542
2004	541	5	0	0	0	0	43	25	3000	1000	2000	2000	18000	0	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	0	0	0	73	1	16	1	1	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	0	0	0	43	25	3000	1000	2000	2000	18000	0	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	0	0	0	73	1	16	1	1	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	0	0	0	43	25	3000	1000	2000	2000	18000	1	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	0	0	0	73	1	16	1	1	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	0	0	0	43	25	3000	1000	2000	2000	18000	1	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	0	0	0	73	1	16	1	1	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	0	0	0	43	25	3000	1000	2000	2000	18000	0	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	0	0	0	73	1	16	1	1	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	0	0	0	43	25	3000	1000	2000	2000	18000	0	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	0	0	0	73	1	16	1	1	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	0	0	0	43	25	3000	1000	2000	2000	18000	0	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	0	0	0	73	1	16	1	1	538	1000	1000	1000	542	542	542	542	542

Test 2: Latency 1->2 roundtrip

Code:

  fcvtpu w0, s0
  fmov d0, x0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 13.0038

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30204	130038	974	0	0	0	0	0	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	1	130013	130038	130064	125476	3	126246	30100	200	10000	20000	200	10000	20000	130038	130038	2	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	0	0	1310	1	2	16	2	2	129525	10000	10000	10000	10100	130039	130039	130039	130077	130077
30204	130047	974	0	0	0	0	0	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	1	130013	130038	130038	125476	3	126246	30100	200	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	0	0	1310	1	2	16	2	2	129525	10000	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	974	0	0	0	0	0	0	130027	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	1	130013	130038	130038	125476	3	126246	30100	200	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	0	0	1310	1	2	16	2	2	129525	10000	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	974	0	0	0	0	0	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	0	130013	130038	130038	125476	3	126246	30100	200	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	0	0	1310	1	2	16	2	2	129525	10000	10000	10000	10100	130039	130039	130039	130039	130039
30204	130040	974	0	0	0	0	0	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	1	130013	130038	130043	125476	3	126246	30100	200	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	0	0	1310	1	2	16	2	2	129525	10000	10000	10000	10100	130039	130111	130053	130039	130039
30204	130038	974	0	0	0	0	0	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	1	130013	130038	130038	125476	3	126246	30100	200	10060	20000	200	10000	20000	130038	130041	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	0	0	1310	1	2	16	2	2	129525	10000	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	974	0	0	0	0	0	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	0	130013	130038	130038	125476	3	126246	30100	202	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	0	0	1310	1	2	16	2	2	129525	10000	10000	10000	10100	130039	130039	130039	130039	130039
30204	130038	974	0	0	0	0	0	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	0	130013	130038	130038	125476	3	126246	30100	200	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	3	0	0	0	0	1310	1	2	16	2	2	129525	10000	10000	10000	10100	130039	130039	130039	130039	130039
30205	130096	974	0	0	0	0	0	0	130023	119417	25	40100	10100	20004	10000	100	20000	10000	500	6214979	14801266	1	130013	130038	130038	125476	3	126246	30100	200	10000	20000	200	10000	20000	130038	130039	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	0	0	1310	1	2	16	2	2	129525	10000	10000	10000	10100	130072	130039	130039	130039	130039
30204	130038	975	0	0	0	0	0	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	0	130013	130038	130038	125476	3	126246	30100	200	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	0	10000	0	0	0	0	0	0	0	1310	1	2	16	2	2	129525	10000	10000	10000	10100	130039	130039	130039	130039	130039

1000 unrolls and 10 iterations

Result (median cycles for code): 13.0038

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	1e	1f	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30024	130038	974	0	0	0	0	216	0	130108	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	1	130023	130038	130041	125637	3	126268	30182	20	10000	20000	20	10000	20000	130038	130043	1	1	20021	10	9	10	10010	10000	10	10000	0	0	3	0	0	1270	1	16	1	1	129526	10000	10000	10000	10010	130039	130039	130039	130040	130040
30024	130038	974	0	0	0	0	177	0	130023	120780	859	40244	10059	20120	10073	13	24425	11862	65	6303397	15014119	1	130013	130040	130038	125551	100	126236	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	10000	0	0	3	0	0	1270	1	16	1	1	129525	10000	10000	10000	10010	130039	130039	130039	130046	130039
30024	130038	974	0	0	0	0	48	352	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	1	130013	130038	130040	125500	3	126268	30010	20	10000	20000	20	10000	20491	130040	130038	1	1	20021	10	9	10	10010	10000	10	10000	0	0	0	0	0	1270	1	16	1	1	129525	10000	10000	10000	10010	130039	130039	130039	130039	130039
30024	130038	974	0	0	0	0	603	0	130023	119417	25	40010	10017	20000	10000	10	20000	10000	50	6223695	14800025	0	130013	130038	130038	125498	3	126268	30010	20	10000	20241	20	10000	20000	130041	130039	5	1	20021	10	9	10	10010	10000	10	10000	4	0	0	0	0	1270	1	48	1	1	129525	10000	10000	10000	10010	130039	130039	130039	130039	130039
30024	130038	974	0	0	0	0	0	0	130023	119417	25	40010	10016	20000	10000	10	20000	10000	50	6215123	14800025	0	130013	130038	130038	125498	3	126328	30010	20	10000	20000	20	10000	20485	130038	130038	1	1	20021	10	9	10	10010	10000	10	10000	1	0	0	0	0	1270	1	16	1	1	129525	10000	10000	10000	10010	130039	130039	130039	130039	130039
30024	130038	974	0	0	0	0	0	0	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	0	130015	130038	130038	125498	3	126472	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	10000	0	0	0	0	0	1270	1	16	1	1	129525	10000	10000	10000	10010	130039	130039	130039	130039	130039
30024	130038	975	0	0	0	0	0	0	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	0	130013	130038	130038	125498	3	126268	30010	20	10000	20000	20	10000	20000	130040	130039	5	1	20021	10	9	10	10010	10000	10	10000	0	0	3	0	0	1270	1	16	1	1	129525	10000	10000	10000	10010	130039	130039	130039	130039	130039
30024	130038	974	0	0	0	0	0	0	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	0	130013	130038	130038	125498	3	126268	30010	20	10000	20000	20	10000	20481	130038	130038	1	1	20021	10	9	10	10010	10000	10	10000	3	0	0	0	0	1270	2	24	1	1	129527	10000	10000	10000	10010	130039	130039	130039	130039	130039
30024	130038	974	0	0	0	0	0	0	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	0	130013	130038	130038	125498	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	10000	0	0	0	0	0	1270	1	16	1	1	129525	10000	10000	10000	10010	130039	130039	130039	130039	130039
30024	130038	974	0	0	0	0	0	0	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	0	130013	130038	130038	125498	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	10000	0	0	0	0	0	1270	1	16	1	1	129525	10000	10000	10000	10010	130040	130039	130039	130039	130039

Test 3: throughput

Count: 8

Code:

  fcvtpu w0, s8
  fcvtpu w1, s8
  fcvtpu w2, s8
  fcvtpu w3, s8
  fcvtpu w4, s8
  fcvtpu w5, s8
  fcvtpu w6, s8
  fcvtpu w7, s8

Initialization

  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	a9	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	ea	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	40041	310	0	1	1	0	0	0	0	0	0	32	25	240104	80100	160004	100	160020	500	1440132	0	40022	40041	40041	19977	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	1	0	0	1	1	1	5117	1	16	1	1	40038	80000	0	80000	80100	40124	40042	40042	40042	40042
160204	40041	311	0	1	1	0	0	0	0	0	0	32	25	240104	80100	160004	100	160020	500	1440132	0	40022	40041	40041	19977	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	0	0	0	1	1	1	5117	1	70	1	1	40038	80000	0	80000	80100	40042	40042	40042	40042	40042
160204	40041	310	0	1	1	0	0	0	0	0	0	32	25	240104	80100	160004	100	160020	500	1440132	0	40022	40041	40041	19977	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	0	0	0	1	1	1	5117	1	16	1	1	40038	80000	0	80000	80100	40042	40042	40042	40042	40042
160204	40041	310	0	1	1	0	0	0	0	0	0	60	25	240104	80100	160004	100	160020	500	1440132	0	40022	40041	40041	19977	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	1	0	3	1	1	1	5117	1	16	1	1	40038	80000	0	80000	80100	40042	40042	40042	40042	40042
160204	40041	310	0	1	1	0	0	0	12	0	0	697	25	240104	80100	160004	100	160020	500	1440132	0	40022	40041	40041	19977	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	0	0	0	1	1	1	5117	1	16	1	1	40038	80000	0	80000	80100	40042	40042	40042	40042	40042
160204	40041	310	0	1	1	0	0	0	0	0	0	32	25	240104	80100	160004	100	160020	500	1440132	0	40022	40041	40041	19977	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	0	1	0	1	1	1	5117	1	16	1	1	40038	80000	0	80000	80100	40042	40042	40042	40042	40042
160204	40041	311	0	1	1	0	0	0	0	0	0	32	25	240104	80100	160004	100	160020	500	1440132	0	40865	41051	41058	20270	103	20577	162832	204	162702	202	162926	41081	41159	15	1	80201	100	99	100	80100	100	2	0	1	0	8753	1	1	1	5343	1	142	2	1	40947	81418	0	80000	80100	40042	40205	41150	41165	41147
160204	41239	318	0	1	1	0	0	1	9	0	0	10777	91	243310	81150	161376	104	161868	500	1461696	0	40785	41128	40915	20284	56	20670	163168	202	162906	202	161660	41151	41167	14	1	80201	100	99	100	80100	100	0	2	0	7	9453	1	1	1	5377	1	151	1	1	41019	80000	0	80000	80100	40042	40042	40042	40042	40042
160204	40123	311	0	1	1	0	13	9	1332	264	0	7388	261	244192	81370	162940	106	163104	596	1469546	0	41106	41285	41310	20355	129	20400	163386	200	163380	206	162286	41242	41388	18	1	80201	100	99	100	80100	100	0	0	0	0	11335	1	1	1	5117	2	106	1	1	40752	81250	0	80000	80100	41145	41140	41171	40756	41071
160204	41066	319	0	1	1	0	9	9	1068	968	0	592	141	243304	80585	162128	102	161486	500	1460270	0	40405	40742	40041	19977	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	1	0	0	1	1	1	5231	2	79	1	1	40496	81258	0	80000	80100	40278	40827	41064	40763	40853

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	rob full (74)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	c2	cd	cf	d2	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	40055	300	15	42	72	240010	80010	160000	10	160000	50	1440000	0	40022	40041	40041	19996	0	3	20206	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	5020	0	11	16	13	11	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	300	0	707	25	240010	80010	160000	10	160000	50	1440000	0	40022	40041	40041	19996	0	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	5020	0	13	16	11	11	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	299	0	64	25	240010	80010	160000	10	160000	50	1440000	0	40022	40041	40041	19996	0	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	5020	0	12	16	11	11	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	299	0	802	25	240010	80010	160000	10	160000	50	1440000	0	40022	40041	40041	19996	0	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	5020	0	10	16	11	13	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	300	0	42	25	240010	80010	160000	10	160000	50	1440000	0	40022	40041	40041	19996	0	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	5020	0	12	16	9	14	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	310	0	42	25	240010	80010	160000	10	160000	50	1440000	0	40022	40041	40041	19996	0	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	1	0	0	0	5020	0	10	16	11	10	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	300	0	42	25	240010	80010	160000	10	160000	50	1440000	1	40022	40041	40041	19996	0	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	5020	0	10	16	13	11	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	299	0	42	25	240010	80010	160000	10	160000	50	1440000	0	40022	40041	40041	19996	0	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	5020	0	11	16	13	10	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	300	0	42	25	240010	80010	160000	10	160000	50	1440000	0	40022	40041	40041	19996	0	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	5020	0	16	16	10	11	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	300	0	42	25	240010	80010	160000	10	160000	50	1440000	0	40022	40041	40041	19996	0	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	0	0	0	0	5020	0	13	16	13	11	40038	80000	80000	80010	40042	40042	40042	40042	40042

FCVTPU (scalar, S to W)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations