Apple M1 Microarchitecture Research by Dougall Johnson

Firestorm: Overview | Base Instructions | SIMD and FP Instructions
Icestorm:  Overview | Base Instructions | SIMD and FP Instructions

FCVTPU (scalar, S to X)

Test 1: uops

Code:

  fcvtpu x0, s0
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 3.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 2.000

retire (01)cycle (02)031e3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch fp/simd (57)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op fp/simd (7e)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst integer (97)a8accfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
2004541408025300010002000200018000052254154124832742000200020005415411110011000107311611538100010001000542542542542542
2004541404325300010002000200018000152254154124832742000200020005415411110011000007311611538100010001000542542542542542
2004541404325300010002000200018000152254154124832742000200020005415411110011000007311611538100010001000542542542542542
2004541494325300010002000200018000152254154124832742000200020005415411110011000007311611538100010001000542542542542542
2004541494325300010002000200018000052254154124832742192200020005415411110011000007311611538100010001000542542542542542
2004541404325300010002000200018000152254154124832742000200020005415411110011000007311611538100010001000542542542542542
2004541404325300010002000200018000052254154124832742000200020005415411110011000007311611538100010001000542542542542542
2004541404325300010002000200018000052254154124832742000200020005415411110011000007311611538100010001000542542542542542
2004541404325300010002000200018000052254154124832742000200020005415411110011000007311611538100010001000542542542542542
2004541404325300010002000200018000152254154124832742000200020005415411110011000007311611538100010001000542542542542542

Test 2: Latency 1->2 roundtrip

Code:

  fcvtpu x0, s0
  fmov d0, x0
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 13.0038

retire (01)cycle (02)03080b18191e3f4f51inst issue (52)~issue int (53)~issue fp/simd (54)~issue ld/st (55)~dispatch int (56)~dispatch fp/simd (57)~dispatch ld/st (58)huge thing int (59)huge thing ld/st (5a)huge thing fp/simd (5b)60696b6d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op ld/st (7d)~map op fp/simd (7e)~map lookup int (7f)~map lookup ld/st (80)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa1a6a8a9acc2c5cfd0d5d6ddinst fetch restart (de)e0? int output thing (e9)ld/st retires (ed)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
3020413003897400000130023119417254010010100200001000010020000100005006214979148010340130013013004413004112547631262503010020010000200002001000020000130038130038112020110099100101001000010001000000300131013162212952510000100001000010100130039130039130039130039130039
3020413003897400000130023119417254010010100200001000010020000100005006214979148010340130013013003813003812547631263073010020010000200002001000020000130038130038112020110099100101001000010001000010000131012162212952510000100001000010100130039130039130039130039130039
3020413003897400000130023119417254010010100200001000010020000100005006214979148010340130013013003813003812547631263023010020010000200002001000020000130038130038112020110099100101001000010001000012020131012512212952510000100001000010100130039130039130039130039130620
302041300389741017294130023119420254010010100200001000010020000100005006214979148010340130016013003813003912547631262463010020010000200002001000020000130038130038112020110099100101001000010001000000000131012162212952510000100001000010100130039130039130039130039130039
302041300389740000013002311941725401001010020000100001002000010000500621497914801034013001301300381300381254763126273301002001000020000200100002000013003813003811202011009910010100100001000100003018000131012162212952510000100001000010100130040130041130039130039130039
3020413003897400000130023119417254010010100200001000010020000100005006214979148010340130013013003813003812547631262893010020010000200002001000020000130038130038112020110099100101001000010001000000000131012162212952510000100001000010100130039130039130039130039130039
3020413003897400000130023119417254010010100200001000010020000100005006214979148010341130013013003813003812547631262843010020010000200002021000020000130038130038112020110099100101001000010021000000000131013162212952810000100001000010100130039130039130039130039130040
3020413003897400000130023119417254010010100200001000010020000100005006215123148011501130013013003813003812547661262963026620010065200002001000020000130038130038112020110099100101001000010001000000600131012162212952510000100001000010100130039130039130039130039130039
3020413003897400000130023119417254010010100200001000010020000100005006214979148019570130013013004513004112547631262473010020010000200002001000020000130038130038112020110099100101001000010001000000000131012162212952510000100001000010100130039130039130039130039130039
30204130038974000015130023119417254010010100200001000010020000100005006214979148010340130013013003813003812547631262463026620010000200002001000020000130038130044112020110099100101001000010001000000000131012162212952510000100001000010100130039130039130039130039130039

1000 unrolls and 10 iterations

Result (median cycles for code): 13.0038

retire (01)cycle (02)0318191e1f3f4f51inst issue (52)~issue int (53)~issue fp/simd (54)~issue ld/st (55)~dispatch int (56)~dispatch fp/simd (57)~dispatch ld/st (58)huge thing int (59)huge thing ld/st (5a)huge thing fp/simd (5b)60696b6d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op ld/st (7d)~map op fp/simd (7e)~map lookup int (7f)~map lookup ld/st (80)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa0a1a6a7a8a9acafc2c5cfd5d6ddinst fetch restart (de)e0? int output thing (e9)ld/st retires (ed)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
3002413003810080000130023119417254001010010200001000010200001000050621497914800025013001301300381300381254983126268300102010000200002010000200001300381300381120021109101001010000100010000000000012703161112952510000100001000010010130039130039130039130039130039
3002413003810080000130023119417254001010010200001000010200001000050621497914800025113001301300381300381254983126268300102010000200002010000200001300381300381120021109101001010000100010000000000012701161112952510000100001000010010130039130039130039130039130039
300241300389740000130023119419254001010010200001000010200001000050621497914800025113001301300381300381254983126268300102010000200002010000200001300381300381120021109101001010000100010000000000012701161112952510000100001000010010130039130039130039130039130039
30024130038974000013002311941725400101001020000100001020000100005062149791480002501300130130038130038125498312626830010201000020000201000020000130038130038112002110910100101000010001000000022027330012701161112952510000100001000010010130039130039130039130039130039
300241300389740000130023119417254001010010200001000010200001000050621497914800025013001301300381300381254983126268300102010000200002010000200001300381300381120021109101001010000100010000000000012701161212952510000100001000010010130039130039130039130039130039
300241300389730000130023119417254001010010200001000010200001000050621497914800025113001301300381300381254983126268300102010000200002010000200001300381300381120021109101001010000100010000000000012701161112952510000100001000010010130063130043130039130039130039
300241300389740000130023119417254001010010200001000010200001000050621497914800025113004401300381300381254983126268300102010000200002010000200001300381300381120021109101001010000100010000000000012701161112952510000100001000010010130039130039130039130039130039
300241300389740000130023119417254001010010200001000010200001000050621497914800025113005901300381300381254983126268300102010000200002010000200001300381300381120021109101001010000100010000000000012701162112952510000100001000010010130039130039130039130039130039
300241300389740000130023119417254001010010200001000010200001000050621593914800025013001501300381300381255013126268300102010000200002010000200001300381300381120022109101001010000100010000000000012701161212952510000100001000010010130042130039130039130039130039
300241300389740000130023119417254001010010200001000010200001000050621497914800025113001301300381300381254983126268300102010000200002010000200001300381300381120021109101001010000100010000020000012701161112952510000100001000010010130039130039130039130039130039

Test 3: throughput

Count: 8

Code:

  fcvtpu x0, s8
  fcvtpu x1, s8
  fcvtpu x2, s8
  fcvtpu x3, s8
  fcvtpu x4, s8
  fcvtpu x5, s8
  fcvtpu x6, s8
  fcvtpu x7, s8
  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5006

retire (01)cycle (02)030b1e3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)9fa0a8acc5branch mispredict (cb)cdcfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
160204400643000783225240104801001600041001600205001440132140022400414004119977619992160120200160032200160032400414004111802011009910080100100000111511701600400388000080000801004004240042400424004240042
16020440041300003225240104801001600041001600205001440132140022400414004119977619992160120200160032200160032400414004111802011009910080100100000111511701600400388000080000801004004240042400424004240042
160204400412990032252401048010016000410016002050014401321400224004140041199776199921601202001600322001600324004140041118020110099100801001000380111511701600400388000080000801004004240042400424004240042
160204400412990543225240104801001600041001600205001440132140022400414004119977619992160120200160032200160032400414004111802011009910080100100000111511701600400388000080000801004004240042400424004240042
160204400413000213225240104801001600041001600205001440132140022400414004119977619992160120200160032200160032400414004111802011009910080100100000111511701600400388000080000801004004240042400424004240042
16020440041300003225240104801001600041001600205001440132140022400414004119977619992160120200160032200160032400414004111802011009910080100100000111511701600400388000080000801004004240042400424004240042
16020440041300003225240104801001600041001600205001440132140022400414004119977619992160120200160032200160032400414004111802011009910080100100000111511701600400388000080000801004004240042400424004240126
160204400412990123225240104801001600041001600205001440132140022400414004119977619992160120200160032200160032400414004111802011009910080100100000111511701600400388000080000801004004240042400424004240042
16020440041300033225240104801001600041001600205001440132140022400414004119977619992160120200160032200160032400414004111802011009910080100100000111511701600400388000080000801004004240042400424004240042
160204400413000543225240104801001600041001600205001440132140022400414004119977619992160120200160032200160032400414004111802011009910080100100000111511701600400388000080000801004004240042400424004240042

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

retire (01)cycle (02)03081e3a3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)9fa6a8accfd5d6dbddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
160024400553000004472524001080010160000101600005014400001400224004140041199963200211600102016000020160000400414004111800211091080010100005020616035400388000080000800104004240042400424004240042
16002440041300000422524001080010160000101600005014400001400224004140041199963200211600102016000020160000400414012911800211091080010100005020616064400388000080000800104004240042400424004240042
16002440041300000422524001080191160000101600005014400000400224004140041199963200211600102016000020160000400414004111800211091080010100035020616084400388000080000800104004240042400424004240042
160024400412990120632524001080010160000101600005014400000400224004140041199963200211600102016000020160000400414004111800211091080010100105020616075400388000080000800104004240042400424004240042
16002440041300137506617124001080010160202101600005014400001400224004140041199963200211600102016000020160000400414004111800211091080010100035020516046400388000080000800104004240042400424004240042
160024400413000007072524001080010160000101600005014400000400224004140041199963200211600102016000020160000400414004111800211091080010100005020416046400388000080000800104004240042400424004240042
160024400413000120422524001080010160000101600005014400000400224004140041199963200211600102016000020160000400414004111800211091080010102335020616065400388000080000800104004240042400424004240042
16002440041300000422524001080010160000101600005014400000400224004140041199963200211600102016000020160000400414004111800211091080010100005020716086400388000080000800104004240042400424004240042
16002440041299000422524001080010160000101600005014400000400224004140041199963200211600102016000020160000400414004111800211091080010100005020516077400388000080000800104004240042400424004240042
16002440041300000422524001080010160000101600005014400000400224004140041199963200211602142016000020160000400414004111800211091080010100005020616066400388000080000800104004240042400424004240042