Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FCVTPU (vector, 8H)

Test 1: uops

Code:

  fcvtpu v0.8h, v0.8h
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03l2 tlb miss data (0b)18191e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d tlb access (a0)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100430372400042612547251000100010003981603018303730372414328951000100010003037303711100110000000073116112629100030383038303830383038
10043037240000612547251000100010003981603018303730372414328951000100010003037303711100110000003073116112629100030383038303830383038
10043037240000612547251000100010003981603018303730372414328951000100010003037303711100110000000073116112629100030383038303830383038
10043037240000612547251000100010003981603018303730372414328951000100010003037303711100110000000073116112629100030383038303830383038
10043037240000612547251000100010003981603018303730372414328951000100010003037303711100110000000073116112629100030383038303830383038
10043037240000612547251000100010003981603018303730372414328951000100010003037303711100110000000073116112629100030383038303830383038
10043037240000612547251000100010003981603018303730372414328951000100010003037303711100110000000073116112629100030383038303830383038
10043037240009612547251000100010003981603018303730372414328951000100010003037303711100110000000073116112629100030383038303830383038
10043037230000612547251000100010003981603018303730372414328951000100010003037303711100110000003073116112629100030383038303830383038
100430372300001032547251000100010003981603018303730372414328951000100010003037303711100110000000073116112629100030383038303830383038

Test 2: Latency 1->2

Code:

  fcvtpu v0.8h, v0.8h
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)09181e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)cfd5map dispatch bubble (d6)ddfetch restart (de)e0eb? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043003722500006129547251010010010000100100005004277160130018300373003728264328745101002001000020010000300373003711102011009910010010000100071011611296330100001003003830038300383003830038
102043003722400006129547251010010010000100100005004277160030018300373003728264328745101002001000020010000300373003711102011009910010010000100071011611296330100001003003830038300383003830038
102043003722500006129547251010010010000100100005004277160030018300373003728264328745101002001000020010000300373003711102011009910010010000100071011611296330100001003003830038300383003830038
102043003722500006129547251010010010000100100005004277160030018300373003728264328745101002001000020010000300373003711102011009910010010000100071011611296330100001003003830038300383003830038
102043003722500006129547251010010010000100100005004277160030018300373003728264328745101002001000020010000300373003711102011009910010010000100071011611296330100001003003830038300383003830038
102043003722500006129547251010010010000100100005004277160030018300373003728264328745101002001000020010000300373003711102011009910010010000100071011611297050100001003003830038300383003830038
102043003722500006129547251010010010000100100005004277160030018300373003728264328745101002001000020010000300373003711102011009910010010000100071011611296330100001003003830038300383003830038
102043003722500006129547251010010010000100100005004277160030018300373003728264328745101002001000020010000300373003711102011009910010010000100071011611296330100001003003830038300383003830038
102043003722500006129547251010010010000100100005004277160030018300373003728264328745101002001000020010000300373003711102011009910010010000100071011611296330100001003003830038300383003830038
102043003722500006129547251010010010000100100005004277160130018300373003728264328745101002001000020010000300373003711102011009910010010000100071011611296330100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024300372250000061295472510010101000010100005042771601300183003730037282863287671001020100002010000300373003711100211091010100001000000640316332962910000103003830084300863003830038
100243003722400000300295472510020111000010100005042771600300183003730037282863287671001020100002010000300373003711100211091010100001000000640316332962910000103003830038300383003830038
10024300372250100061295472510010101000010100005042771600300183003730037282863287671001020100002010000300373003711100211091010100001000000640316332962910000103003830038300383003830038
10024300372250000061295472510010101000010100005042771601300183003730037282863287671001020100002010000300373003711100211091010100001000630640316332962910000103003830038300383003830038
100243003723200090520295472510010101000013100005042785120300183003730037282863287671001020100002010000300373003711100211091010100001000430640316332962910000103003830038300383003830038
10024300372250003061295472510010101000010100005042771601300183003730037282863287671001020100002010000300853008511100211091010100001002190661316332962910000103003830085300383003830085
100243003722600012061295472510010101000010100005042771600300183003730037282863287671001022100002010000300373003711100211091010100001000000640316332962910000103003830038300383003830038
10024300372250000061295472510010101000010100005042771600300543003730037282863287671001020100002010000300373003711100211091010100001000000640316332962910000103003830038300383003830038
10024300372250000061295472510010101000010100005042771600300183003730037282863287671001020100002010000300373003711100211091010100001000000640316332962910000103003830038300383003830038
10024300372250000061295472510010101000010100005042771601300183003730037282863287671001020100002010000300373003711100211091010100001000030640316332962910000103003830038300383003830038

Test 3: throughput

Count: 8

Code:

  fcvtpu v0.8h, v8.8h
  fcvtpu v1.8h, v8.8h
  fcvtpu v2.8h, v8.8h
  fcvtpu v3.8h, v8.8h
  fcvtpu v4.8h, v8.8h
  fcvtpu v5.8h, v8.8h
  fcvtpu v6.8h, v8.8h
  fcvtpu v7.8h, v8.8h
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03181e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
802042003915000020025801081008000810080020500640132020020200392003999770699908012020080032200800322003920039118020110099100100800001000011151180160020036800001002004020040200402004020040
80204200391500003025801081008000810080020500640132020020200392003999770699908012020080032200800322003920039118020110099100100800001000011151180160020036800001002004020040200402004020040
80204200391500003025801081008000810080020500640132020020200392003999770699908012020080032200800322003920039118020110099100100800001000011151180160020036800001002004020040200402004020040
8020420039150057252119825801081008000810080020500640132020020200392003999770699908012020080032200800322003920195118020110099100100800001000011151180160020036800001002004020040200402004020040
8020420039150012088925801081008000810080020500640132020020200392003999770699908012020080032200800322003920039118020110099100100800001000011151180160020036800001002004020040200402004020040
802042003915003303025801081008000810080020500640132020020200392003999770699908012020080032200800322003920039118020110099100100800001000011151180160020036800001002004020040200402004020040
80204200391500003025801081008000810080020500640132120020200392003999770699908012020080032200800322003920039118020110099100100800001000011151180160020036800001002004020040200402004020040
80204200391500005325801081008000810080020500640132020020200392003999770699908012020080032200800322003920039118020110099100100800001001011151180160020036800001002004020040200402004020040
80204200391500003025801081008000810080020500640132020020200392003999770699908012020080032200800322003920039118020110099100100800001000011151180160020036800001002004020040200402004020040
802042003915000037025801081008000810080020500640132020020200392003999770699908012020080032200800322003920039118020110099100100800001000011151180160020036800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8002420051150004025800101080000108000050640000012002020039200399996310019800102080000208000020039200391180021109101080000100050201416372003680000102004020040200402004020040
800242003915000402580010108000010800005064000000200202003920039999631001980010208014020800002003920039118002110910108000010065020316732003680000102004020040200402004020040
8002420039155001522580010108000010800005064000000200202003920039999631001980010208000020800002003920039118002210910108000010005020716732003680000102004020040200402004020040
800242003915000402580010108000010800005064000001200202003920039999631001980010208000020800002003920039118002110910108000010005020416332003680000102004020040200402004020040
800242003915000402580010108000010800005064000001200202003920039999631001980010208000020800002003920039118002110910108000010005020416372003680000102004020040200402004020040
800242003915000402580010108000010800005064000000200202003920039999631001980010208000020800002003920039118002110910108000010005020416332003680000102004020040200402004020040
800242003915000402580010108000010800005064000000200202003920039999631001980010208000020800002003920039118002110910108000010035020316332003680000102004020040200402004020040
800242003915000402580010108000010800005064000000200202003920039999631001980010208000020800002003920039118002110910108000010005020316372003680000102004020040200402004020040
800242003915060402580010108000010800005064000000200202003920039999631001980010208000020800002003920039118002110910108000010005020716732003680000102004020040200402004020040
80024200391572101392580010108000010800005064000000200202003920039999631001980010208000020800002003920039118002110910108000010135020316332003680000102004020040200402004020040