Firestorm: FCVTXN2 (vector, 2D) measurements

Code:

  fcvtxn2 v0.4s, v1.2d

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	19	1e	3f	4e	51	schedule uop (52)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst simd alu (9a)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	f5	f6	f7	f8	fd
1004	3037	23	0	0	0	84	2548	25	1000	1000	1000	398313	1	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	3	16	2	2	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	1	0	73	2	16	2	2	2630	1000	3038	3038	3038	3038	3038
1004	3037	24	0	0	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	2	16	2	2	2702	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	2	16	2	2	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	0	298	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	3	73	2	16	2	2	2630	1000	3038	3038	3038	3038	3038
1004	3037	24	0	0	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	2	16	2	2	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	0	84	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	2	16	2	2	2700	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	2	16	2	2	2630	1000	3038	3038	3038	3038	3038
1004	3037	23	0	0	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	2	16	2	2	2630	1000	3038	3038	3038	3038	3038
1004	3037	24	0	0	0	61	2548	25	1000	1000	1000	398313	0	3018	3037	3037	2415	3	2895	1000	1000	2000	3037	3037	1	1	1001	1000	0	0	73	2	16	2	2	2630	1000	3038	3038	3038	3038	3038

Test 2: Latency 1->1

Code:

  fcvtxn2 v0.4s, v1.2d

Initialization

  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	18	19	1e	1f	3f	4c	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	l1d cache miss ld nonspec (bf)	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	241	0	0	0	0	0	0	61	0	29548	25	10100	100	10000	100	10000	500	4277313	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	0	0	710	2	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	233	0	0	0	0	12	0	103	0	29548	25	10100	100	10000	100	10000	500	4277313	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	0	0	785	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	232	0	1	0	0	0	0	89	0	29548	25	10100	100	10000	100	10000	500	4277313	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10205	30037	233	0	0	0	0	0	0	61	0	29548	25	10100	100	10000	100	10000	500	4277313	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	233	0	0	0	0	0	0	431	0	29548	25	10100	100	10000	100	10000	500	4277313	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	233	0	0	0	0	0	0	61	0	29548	25	10100	100	10000	100	10000	500	4277313	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	232	0	0	0	0	0	0	477	0	29548	25	10100	100	10000	100	10000	500	4277313	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30085
10204	30037	233	0	0	0	0	0	0	61	0	29548	25	10100	100	10000	100	10000	500	4277313	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	3	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	232	0	0	0	0	0	0	61	0	29548	25	10100	100	10000	100	10000	500	4277313	30018	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	0	0	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038
10204	30037	233	0	0	0	0	0	0	61	0	29548	25	10100	100	10000	100	10000	500	4277313	30065	30037	30037	28265	3	28745	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	2	0	0	0	0	0	0	0	710	1	16	1	1	29634	0	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	18	19	1e	1f	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch call (8e)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	branch mispred nonspec (cb)	cf	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	241	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	26	28767	10010	20	0	10000	20	20000	30037	30037	1	1	10021	10	0	9	10	10	10000	10	0	0	0	1	0	9	0	640	0	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	233	0	0	0	12	0	103	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	0	10000	20	20000	30037	30037	1	1	10021	10	0	9	10	10	10000	10	0	0	0	0	0	0	0	640	0	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	233	0	0	0	0	0	536	29548	25	10010	10	10016	10	10000	60	4277313	1	30018	30037	30037	28287	3	28767	10010	20	0	10000	20	20000	30037	30037	1	1	10021	10	0	9	10	10	10000	10	0	0	0	0	0	0	0	640	0	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	241	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	0	10000	20	20000	30037	30037	1	1	10021	10	0	9	10	10	10000	10	0	0	0	0	0	0	0	640	0	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	260	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	0	10000	20	20000	30037	30037	1	1	10021	10	0	9	10	10	10000	10	0	0	0	0	0	0	0	640	0	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	241	0	0	0	9	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	0	10000	20	20000	30037	30037	1	1	10021	10	0	9	10	10	10000	10	0	0	0	0	0	0	0	640	0	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	241	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	0	10000	20	20000	30037	30037	1	1	10021	10	0	9	10	10	10000	10	0	0	0	0	0	0	0	640	0	3	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	241	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	0	10000	20	20000	30037	30037	1	1	10021	10	0	9	10	10	10000	10	0	0	0	0	0	0	0	640	0	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	232	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	1	30018	30037	30037	28287	3	28767	10010	20	0	10000	20	20000	30037	30037	1	1	10021	10	0	9	10	10	10000	10	0	0	0	0	0	0	0	640	0	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038
10024	30037	233	0	0	0	0	0	61	29548	25	10010	10	10000	10	10000	50	4277313	0	30018	30037	30037	28287	3	28767	10010	20	0	10000	20	20000	30037	30037	1	1	10021	10	0	9	10	10	10000	10	0	0	0	0	0	0	0	640	0	2	16	2	2	29630	0	10000	10	30038	30038	30038	30038	30038

Test 3: Latency 1->2

Code:

  fcvtxn2 v0.4s, v0.2d

Initialization

  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	1e	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10204	30037	241	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	0	30018	30037	30037	28271	7	28741	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	1	1	1	718	2	24	2	2	29629	0	10000	100	30038	30038	30038	30038	30038
10204	30037	232	0	1	125	29547	25	10100	100	10000	100	10000	500	4277160	0	30018	30037	30037	28252	6	28733	10100	200	10000	200	20000	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	1	1	1	718	0	16	0	0	29645	0	10000	100	30038	30038	30038	30038	30038
10204	30037	232	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	1	30018	30037	30037	28271	7	28741	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	3	1	1	1	717	0	16	0	0	29646	0	10000	100	30038	30038	30038	30038	30038
10204	30037	232	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	0	30018	30037	30037	28271	6	28740	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	1	1	1	718	0	16	0	0	29645	0	10000	100	30038	30038	30038	30038	30038
10204	30037	233	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	0	30018	30037	30037	28271	6	28740	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	1	1	1	717	0	16	0	0	29681	0	10000	100	30038	30038	30038	30038	30038
10204	30037	233	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	0	30018	30037	30037	28271	6	28740	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	1	1	1	717	0	16	0	0	29645	0	10000	100	30038	30038	30038	30038	30038
10204	30037	233	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	0	30018	30037	30037	28271	7	28740	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	1	1	1	718	0	16	0	0	29645	0	10000	100	30038	30038	30038	30038	30038
10204	30037	232	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	0	30018	30037	30037	28271	7	28740	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	1	0	1	1	1	718	0	16	0	0	29645	0	10000	100	30038	30038	30038	30038	30038
10204	30037	232	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	0	30018	30037	30037	28271	7	28741	10100	200	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	0	0	0	1	1	1	717	0	16	0	0	29646	0	10000	100	30038	30038	30038	30038	30038
10204	30037	233	0	0	61	29547	25	10100	100	10000	100	10000	500	4277160	0	30018	30037	30037	28271	6	28740	10710	202	10008	200	20016	30037	30037	1	1	10201	100	99	100	100	10000	100	0	2	0	0	1	1	1	718	0	16	0	0	29646	0	10000	100	30038	30038	30038	30038	30038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4e	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
10024	30037	225	0	0	0	0	0	0	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	2	16	2	2	29629	0	10000	10	30038	30038	30038	30038	30038
10024	30037	233	0	0	0	0	0	3	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	30037	30037	28333	65	29009	12110	22	11593	24	24322	30698	30509	15	1	10021	10	9	10	10	10000	10	0	0	2	0	2	40720	0	0	952	4	89	5	2	30135	2	10000	10	30701	30782	30453	30654	30323
10024	30700	237	0	0	0	14	14	1848	1232	1	9749	29421	150	10124	12	10112	14	11398	72	4296088	1	30522	30746	30655	28336	63	29044	12232	20	12126	26	23962	30450	30652	14	1	10021	10	9	10	10	10000	10	2	0	0	0	0	0	2	0	936	4	120	2	3	30097	3	10000	10	30747	30746	30751	30603	30744
10024	30699	238	1	0	1	11	12	1848	1232	0	9834	29421	301	10130	12	10112	16	12250	83	4296088	1	30018	30037	30037	28286	63	28955	12262	22	13117	28	24912	30747	30793	16	1	10021	10	9	10	10	10000	10	2	0	0	0	0	39100	0	0	894	4	128	5	4	30190	0	10000	10	30038	30038	30038	30038	30038
10024	30037	233	0	0	0	0	0	0	0	0	265	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	2	16	2	2	29629	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	6	0	0	640	2	16	2	2	29629	0	10000	10	30038	30038	30038	30038	30038
10024	30037	233	0	0	0	0	0	0	0	0	61	29547	44	10010	10	10000	10	10000	50	4277160	1	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	2	16	2	2	29629	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	0	0	61	29547	25	10010	10	10000	10	10148	50	4277160	0	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	2	16	2	2	29629	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	30037	30037	28286	3	28767	10010	24	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	2	16	2	2	29629	0	10000	10	30038	30038	30038	30038	30038
10024	30037	225	0	0	0	0	0	0	0	0	61	29547	25	10010	10	10000	10	10000	50	4277160	0	30018	30037	30037	28286	3	28767	10010	20	10000	20	20000	30037	30037	1	1	10021	10	9	10	10	10000	10	0	0	0	0	0	0	0	0	640	2	16	2	2	29629	0	10000	10	30038	30038	30038	30038	30038

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  fcvtxn2 v0.4s, v8.2d
  movi v1.16b, 0
  fcvtxn2 v1.4s, v8.2d
  movi v2.16b, 0
  fcvtxn2 v2.4s, v8.2d
  movi v3.16b, 0
  fcvtxn2 v3.4s, v8.2d
  movi v4.16b, 0
  fcvtxn2 v4.4s, v8.2d
  movi v5.16b, 0
  fcvtxn2 v5.4s, v8.2d
  movi v6.16b, 0
  fcvtxn2 v6.4s, v8.2d
  movi v7.16b, 0
  fcvtxn2 v7.4s, v8.2d

Initialization

  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	d5	map dispatch bubble (d6)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	20077	151	0	0	0	0	0	29	25	80116	100	80016	100	80028	500	640196	1	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	2	0	0	1	3	1	1	1	10146	1	16	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	0	0	0	29	25	80116	100	80016	100	80028	500	640196	1	20045	20228	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	1	1	1	10119	0	16	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	1	1	0	0	0	29	25	80116	100	80016	100	80028	500	640196	1	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	1	0	1	1	1	10119	0	16	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	0	0	0	29	25	80116	100	80016	100	80028	500	640196	1	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	1	1	1	10119	0	16	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	151	0	0	0	0	0	29	25	80116	100	80016	100	80028	500	640196	1	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	1	1	1	10119	0	16	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	0	0	0	29	25	80116	100	80016	100	80028	500	640196	1	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	1	1	1	10119	0	16	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	0	0	0	29	25	80116	100	80016	100	80028	500	640196	1	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	1	1	1	10119	0	16	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	0	0	0	29	25	80116	100	80016	100	80028	500	640196	1	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	1	1	1	10119	0	16	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	0	0	0	29	25	80116	100	80016	100	80028	500	640196	1	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	1	1	1	10119	0	16	20062	160000	100	20066	20066	20066	20066	20066
160204	20065	150	0	0	0	0	0	29	25	80116	100	80016	100	80028	500	640196	1	20045	20065	20065	6	12	80128	200	80028	200	160056	20065	20065	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	1	1	1	10119	0	16	20062	160000	100	20066	20066	20066	20066	20066

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	61	69	6d	6e	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d cache writeback (a8)	ac	c9	cf	d0	d2	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	ea	ec	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	20093	156	0	12	51	25	80010	10	80000	10	80000	50	640000	0	0	0	20027	20050	20050	3	22	80010	20	0	80000	20	160000	20046	20050	1	1	160021	10	9	10	10	160000	10	0	0	0	10049	3	1	2	24	20	2	1	2	21	8	20047	15	0	160000	10	20047	20054	20047	20047	20047
160024	20046	155	0	408	45	25	80010	10	80000	10	80000	50	640000	1	1	0	20027	20046	20046	3	22	80010	20	0	80000	20	160000	20046	20046	1	1	160021	10	9	10	10	160000	10	0	0	0	10044	8	1	1	22	20	2	1	2	9	21	20043	15	0	160000	10	20047	20047	20047	20047	20047
160024	20046	155	0	324	45	25	80010	10	80000	10	80000	50	640000	1	1	0	20027	20046	20046	3	22	80010	20	0	80000	20	160000	20046	20046	1	1	160021	10	9	10	10	160000	10	0	0	0	10033	3	1	1	9	21	2	1	1	20	9	20043	15	0	160000	10	20047	20047	20047	20047	20047
160024	20046	156	1	0	45	25	80010	10	80000	10	80000	50	640000	1	0	0	20027	20046	20046	3	22	80010	20	0	80000	20	160000	20046	20046	1	1	160021	10	9	10	10	160000	10	0	0	0	10044	11	5	2	20	20	4	1	2	21	21	20043	15	0	160000	10	20047	20051	20047	20047	20051
160024	20046	156	0	354	51	25	80010	10	80000	10	80000	50	640000	0	0	5	20031	20050	20050	3	22	80010	20	0	80000	20	160000	20050	20051	1	1	160021	10	9	10	10	160000	10	0	0	0	10034	6	4	2	9	20	4	1	2	9	20	20043	30	0	160000	10	20047	20047	20051	20047	20051
160024	20046	155	0	279	45	25	80010	10	80000	10	80000	50	640000	0	0	5	20031	20046	20050	3	22	80010	20	0	80000	20	160000	20046	20046	1	1	160021	10	9	10	10	160000	10	0	0	0	10047	8	2	2	7	20	2	2	2	37	7	20044	15	0	160000	10	20049	20051	20047	20047	20047
160024	20046	155	0	39	45	25	80010	10	80000	10	80000	50	640000	1	1	5	20027	20046	20046	3	22	80010	20	0	80000	20	160000	20046	20046	1	1	160021	10	9	10	10	160000	10	0	0	0	10043	8	4	1	20	20	2	1	1	17	6	20043	15	0	160000	10	20047	20047	20047	20047	20047
160024	20046	156	0	396	45	25	80010	10	80000	10	80000	50	640000	1	1	5	20027	20046	20046	3	22	80010	20	0	80136	20	160000	20046	20046	1	1	160021	10	9	10	10	160000	10	0	0	0	10045	8	1	1	20	20	2	1	1	20	21	20043	30	0	160000	10	20047	20047	20047	20047	20047
160024	20046	161	0	0	51	25	80010	10	80000	10	80000	50	640000	1	1	5	20027	20050	20050	3	22	80010	20	0	80000	20	160000	20050	20046	1	1	160021	10	9	10	10	160000	10	0	0	0	10036	6	6	1	20	20	2	1	1	8	20	20043	15	0	160000	10	20047	20047	20047	20051	20051
160024	20046	156	0	12	51	25	80010	10	80000	10	80000	50	640000	0	0	5	20027	20050	20046	3	22	80010	20	0	80000	20	160000	20046	20046	1	1	160021	10	9	10	10	160000	10	0	0	0	10048	11	2	2	22	20	4	1	1	20	21	20043	15	0	160000	10	20047	20047	20047	20051	20047

Test 5: throughput

Count: 16

Code:

  fcvtxn2 v0.4s, v16.2d
  fcvtxn2 v1.4s, v16.2d
  fcvtxn2 v2.4s, v16.2d
  fcvtxn2 v3.4s, v16.2d
  fcvtxn2 v4.4s, v16.2d
  fcvtxn2 v5.4s, v16.2d
  fcvtxn2 v6.4s, v16.2d
  fcvtxn2 v7.4s, v16.2d
  fcvtxn2 v8.4s, v16.2d
  fcvtxn2 v9.4s, v16.2d
  fcvtxn2 v10.4s, v16.2d
  fcvtxn2 v11.4s, v16.2d
  fcvtxn2 v12.4s, v16.2d
  fcvtxn2 v13.4s, v16.2d
  fcvtxn2 v14.4s, v16.2d
  fcvtxn2 v15.4s, v16.2d

Initialization

  movi v16.16b, 17

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2502

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	l2 tlb miss data (0b)	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	l1i cache miss demand (d3)	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	40058	310	0	0	0	204	25	160108	100	160008	100	160020	500	1280132	0	40020	40039	40039	19977	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	1	1	1	10118	0	0	16	0	0	40036	160000	100	40040	40040	40040	40040	40040
160204	40039	311	0	0	0	156	25	160108	100	160008	100	160020	500	1280132	0	40020	40039	40039	19977	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	1	1	1	10118	0	0	16	0	0	40036	160000	100	40040	40040	40040	40040	40040
160204	40039	310	0	0	0	341	25	160108	100	160008	100	160020	500	1280132	0	40020	40039	40039	19977	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	0	2	1	1	1	10118	0	0	16	0	0	40036	160000	100	40040	40040	40040	40040	40040
160204	40039	310	0	0	3	602	25	160108	100	160008	100	160020	500	1280132	0	40020	40039	40039	19977	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	1	1	1	10118	0	0	16	0	0	40036	160000	100	40040	40040	40040	40040	40040
160204	40039	310	0	0	0	644	25	160108	100	160008	100	160020	500	1280132	0	40020	40039	40039	19977	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	1	1	1	10118	0	0	16	0	0	40036	160000	100	40040	40040	40040	40040	40040
160204	40039	310	0	0	0	30	25	160108	100	160008	100	160020	500	1280132	0	40020	40039	40039	19977	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	1	1	1	10118	0	0	16	0	0	40036	160000	100	40040	40040	40040	40040	40040
160204	40039	310	0	0	0	30	25	160108	100	160008	100	160020	500	1280132	0	40020	40039	40039	19977	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	1	1	1	10118	0	0	16	0	0	40036	160000	100	40040	40040	40040	40040	40040
160204	40039	310	0	0	0	30	25	160108	100	160008	100	160020	500	1280132	0	40020	40039	40039	19977	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	1	1	1	10118	0	0	16	0	0	40036	160000	100	40040	40040	40040	40040	40040
160204	40039	310	0	0	0	30	25	160108	100	160008	100	160020	500	1280132	0	40020	40039	40039	19977	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	1	1	1	10118	0	0	16	0	0	40036	160000	100	40040	40040	40040	40040	40040
160204	40039	310	0	0	0	30	25	160108	100	160008	100	160020	500	1280132	0	40020	40039	40039	19977	6	19990	160120	200	160032	200	320064	40039	40039	1	1	160201	100	99	100	100	160000	100	0	0	0	0	0	1	1	1	10118	0	0	16	0	0	40036	160000	100	40040	40040	40040	40040	40040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2502

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk instruction (07)	l2 tlb miss instruction (0a)	0f	1e	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	5f	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d0	d2	l1i cache miss demand (d3)	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	d9	da	db	dd	fetch restart (de)	e0	? int output thing (e9)	ea	eb	ec	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	40039	311	0	0	1	0	0	1	174	25	160010	10	160000	10	160000	50	1280000	1	0	40020	40039	40039	19996	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10022	3	1	1	0	46	17	1	1	1	31	24	40036	0	16	5	0	160000	10	40040	40040	40040	40040	40040
160024	40039	310	0	0	0	0	0	1	499	25	160010	10	160000	10	160000	50	1280000	1	1	40020	40039	40039	19996	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10022	3	1	1	0	31	16	1	1	1	22	32	40036	0	16	5	0	160000	10	40040	40040	40040	40040	40040
160024	40039	310	0	0	1	0	9	0	190	25	160010	10	160000	10	160000	50	1280000	1	1	40020	40039	40039	19996	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10024	6	2	2	0	19	16	3	2	2	32	23	40036	0	31	10	0	160000	10	40040	40040	40040	40040	40040
160024	40039	310	0	1	0	0	0	0	428	25	160010	10	160000	10	160000	50	1280000	0	1	40020	40039	40039	19996	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	3	10025	3	1	1	0	33	16	3	2	1	32	32	40036	0	31	10	0	160000	10	40040	40040	40040	40040	40040
160024	40039	311	0	0	0	0	0	0	426	25	160010	10	160000	10	160000	50	1280000	0	1	40020	40039	40039	19996	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	6	10024	6	2	2	0	32	16	3	2	2	31	32	40036	0	31	10	0	160000	10	40040	40040	40040	40040	40040
160024	40039	311	0	0	1	0	0	1	383	25	160010	10	160000	10	160000	50	1280000	0	0	40020	40039	40039	19996	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10024	6	2	2	0	31	16	3	2	2	21	31	40036	1	31	10	0	160000	10	40040	40040	40040	40040	40040
160025	40570	310	0	0	1	0	0	0	1278	25	160010	10	160000	10	160000	50	1280000	0	1	40020	40039	40039	19996	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	12	10024	3	1	1	0	32	16	1	1	1	24	31	40036	0	21	7	0	160000	10	40040	40040	40040	40040	40040
160024	40039	311	1	0	0	0	12	1	453	25	160010	10	160000	10	160000	50	1280000	1	0	40020	40039	40039	19996	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	3	10023	3	1	1	1	31	16	1	1	1	27	32	40036	0	20	7	0	160000	10	40040	40040	40040	40040	40040
160024	40039	311	1	0	0	0	0	1	420	25	160010	10	160000	10	160000	50	1280000	1	1	40020	40039	40039	19996	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10025	3	1	1	1	32	16	1	1	1	32	32	40036	0	21	6	0	160000	10	40040	40040	40040	40040	40040
160024	40039	310	1	1	1	0	0	0	460	25	160010	10	160000	10	160000	50	1280000	1	0	40020	40039	40039	19996	3	20019	160010	20	160000	20	320000	40039	40039	1	1	160021	10	9	10	10	160000	10	0	0	0	0	10027	6	2	2	1	32	16	2	1	1	31	25	40036	0	21	7	0	160000	10	40040	40040	40040	40040	40040

FCVTXN2 (vector, 2D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations