Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FCVTXN2 (vector, 2D)

Test 1: uops

Code:

  fcvtxn2 v0.4s, v1.2d
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)03mmu table walk data (08)191e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
10043037230008425482510001000100039831313018303730372415328951000100020003037303711100110000073316222630100030383038303830383038
10043037230006125482510001000100039831303018303730372415328951000100020003037303711100110001073216222630100030383038303830383038
10043037240006125482510001000100039831303018303730372415328951000100020003037303711100110000073216222702100030383038303830383038
10043037230006125482510001000100039831303018303730372415328951000100020003037303711100110000073216222630100030383038303830383038
100430372300029825482510001000100039831303018303730372415328951000100020003037303711100110000373216222630100030383038303830383038
10043037240006125482510001000100039831303018303730372415328951000100020003037303711100110000073216222630100030383038303830383038
10043037230008425482510001000100039831303018303730372415328951000100020003037303711100110000073216222700100030383038303830383038
10043037230006125482510001000100039831303018303730372415328951000100020003037303711100110000073216222630100030383038303830383038
10043037230006125482510001000100039831303018303730372415328951000100020003037303711100110000073216222630100030383038303830383038
10043037240006125482510001000100039831303018303730372415328951000100020003037303711100110000073216222630100030383038303830383038

Test 2: Latency 1->1

Code:

  fcvtxn2 v0.4s, v1.2d
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3f4c4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acl1d cache miss ld nonspec (bf)c2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043003724100000061029548251010010010000100100005004277313300183003730037282653287451010020010000200200003003730037111020110099100100100001000000000000071021611296340100001003003830038300383003830038
10204300372330000120103029548251010010010000100100005004277313300183003730037282653287451010020010000200200003003730037111020110099100100100001000000000000078511611296340100001003003830038300383003830038
102043003723201000089029548251010010010000100100005004277313300183003730037282653287451010020010000200200003003730037111020110099100100100001000000000000071011611296340100001003003830038300383003830038
102053003723300000061029548251010010010000100100005004277313300183003730037282653287451010020010000200200003003730037111020110099100100100001000000000000071011611296340100001003003830038300383003830038
1020430037233000000431029548251010010010000100100005004277313300183003730037282653287451010020010000200200003003730037111020110099100100100001000000000000071011611296340100001003003830038300383003830038
102043003723300000061029548251010010010000100100005004277313300183003730037282653287451010020010000200200003003730037111020110099100100100001000000000000071011611296340100001003003830038300383003830038
1020430037232000000477029548251010010010000100100005004277313300183003730037282653287451010020010000200200003003730037111020110099100100100001000000000000071011611296340100001003003830038300383003830085
102043003723300000061029548251010010010000100100005004277313300183003730037282653287451010020010000200200003003730037111020110099100100100001000000030000071011611296340100001003003830038300383003830038
102043003723200000061029548251010010010000100100005004277313300183003730037282653287451010020010000200200003003730037111020110099100100100001000000000000071011611296340100001003003830038300383003830038
102043003723300000061029548251010010010000100100005004277313300653003730037282653287451010020010000200200003003730037111020110099100100100001000002000000071011611296340100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03l2 tlb miss data (0b)18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch call (8e)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acbranch mispred nonspec (cb)cfl1i cache miss demand (d3)d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
100243003724100000612954825100101010000101000050427731313001830037300372828726287671001020010000202000030037300371110021100910101000010000109064002162229630010000103003830038300383003830038
1002430037233000120103295482510010101000010100005042773130300183003730037282873287671001020010000202000030037300371110021100910101000010000000064002162229630010000103003830038300383003830038
100243003723300000536295482510010101001610100006042773131300183003730037282873287671001020010000202000030037300371110021100910101000010000000064002162229630010000103003830038300383003830038
10024300372410000061295482510010101000010100005042773130300183003730037282873287671001020010000202000030037300371110021100910101000010000000064002162229630010000103003830038300383003830038
10024300372600000061295482510010101000010100005042773131300183003730037282873287671001020010000202000030037300371110021100910101000010000000064002162229630010000103003830038300383003830038
10024300372410009061295482510010101000010100005042773130300183003730037282873287671001020010000202000030037300371110021100910101000010000000064002162229630010000103003830038300383003830038
10024300372410000061295482510010101000010100005042773130300183003730037282873287671001020010000202000030037300371110021100910101000010000000064003162229630010000103003830038300383003830038
10024300372410000061295482510010101000010100005042773130300183003730037282873287671001020010000202000030037300371110021100910101000010000000064002162229630010000103003830038300383003830038
10024300372320000061295482510010101000010100005042773131300183003730037282873287671001020010000202000030037300371110021100910101000010000000064002162229630010000103003830038300383003830038
10024300372330000061295482510010101000010100005042773130300183003730037282873287671001020010000202000030037300371110021100910101000010000000064002162229630010000103003830038300383003830038

Test 3: Latency 1->2

Code:

  fcvtxn2 v0.4s, v0.2d
  movi v0.16b, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020430037241006129547251010010010000100100005004277160030018300373003728271728741101002001000820020016300373003711102011009910010010000100000011171822422296290100001003003830038300383003830038
10204300372320112529547251010010010000100100005004277160030018300373003728252628733101002001000020020000300373003711102011009910010010000100000011171801600296450100001003003830038300383003830038
1020430037232006129547251010010010000100100005004277160130018300373003728271728741101002001000820020016300373003711102011009910010010000100000311171701600296460100001003003830038300383003830038
1020430037232006129547251010010010000100100005004277160030018300373003728271628740101002001000820020016300373003711102011009910010010000100000011171801600296450100001003003830038300383003830038
1020430037233006129547251010010010000100100005004277160030018300373003728271628740101002001000820020016300373003711102011009910010010000100000011171701600296810100001003003830038300383003830038
1020430037233006129547251010010010000100100005004277160030018300373003728271628740101002001000820020016300373003711102011009910010010000100000011171701600296450100001003003830038300383003830038
1020430037233006129547251010010010000100100005004277160030018300373003728271728740101002001000820020016300373003711102011009910010010000100000011171801600296450100001003003830038300383003830038
1020430037232006129547251010010010000100100005004277160030018300373003728271728740101002001000820020016300373003711102011009910010010000100001011171801600296450100001003003830038300383003830038
1020430037232006129547251010010010000100100005004277160030018300373003728271728741101002001000820020016300373003711102011009910010010000100000011171701600296460100001003003830038300383003830038
1020430037233006129547251010010010000100100005004277160030018300373003728271628740107102021000820020016300373003711102011009910010010000100020011171801600296460100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
100243003722500000000612954725100101010000101000050427716003001830037300372828632876710010201000020200003003730037111002110910101000010000000006402162229629010000103003830038300383003830038
100243003723300000300612954725100101010000101000050427716003001830037300372833365290091211022115932424322306983050915110021109101010000100020240720009524895230135210000103070130782304533065430323
10024307002370001414184812321974929421150101241210112141139872429608813052230746306552833663290441223220121262623962304503065214110021109101010000102000002093641202330097310000103074730746307513060330744
100243069923810111121848123209834294213011013012101121612250834296088130018300373003728286632895512262221311728249123074730793161100211091010100001020000391000089441285430190010000103003830038300383003830038
1002430037233000000002652954725100101010000101000050427716003001830037300372828632876710010201000020200003003730037111002110910101000010000000006402162229629010000103003830038300383003830038
100243003722500000000612954725100101010000101000050427716003001830037300372828632876710010201000020200003003730037111002110910101000010000006006402162229629010000103003830038300383003830038
100243003723300000000612954744100101010000101000050427716013001830037300372828632876710010201000020200003003730037111002110910101000010000000006402162229629010000103003830038300383003830038
100243003722500000000612954725100101010000101014850427716003001830037300372828632876710010201000020200003003730037111002110910101000010000000006402162229629010000103003830038300383003830038
100243003722500000000612954725100101010000101000050427716003001830037300372828632876710010241000020200003003730037111002110910101000010000000006402162229629010000103003830038300383003830038
100243003722500000000612954725100101010000101000050427716003001830037300372828632876710010201000020200003003730037111002110910101000010000000006402162229629010000103003830038300383003830038

Test 4: throughput

Count: 8

Code:

  movi v0.16b, 0
  fcvtxn2 v0.4s, v8.2d
  movi v1.16b, 0
  fcvtxn2 v1.4s, v8.2d
  movi v2.16b, 0
  fcvtxn2 v2.4s, v8.2d
  movi v3.16b, 0
  fcvtxn2 v3.4s, v8.2d
  movi v4.16b, 0
  fcvtxn2 v4.4s, v8.2d
  movi v5.16b, 0
  fcvtxn2 v5.4s, v8.2d
  movi v6.16b, 0
  fcvtxn2 v6.4s, v8.2d
  movi v7.16b, 0
  fcvtxn2 v7.4s, v8.2d
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2508

retire uop (01)cycle (02)0318191e1f3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
1602042007715100000292580116100800161008002850064019612004520065200656128012820080028200160056200652006511160201100991001001600001002001311110146116200621600001002006620066200662006620066
1602042006515000000292580116100800161008002850064019612004520228200656128012820080028200160056200652006511160201100991001001600001000000011110119016200621600001002006620066200662006620066
1602042006515011000292580116100800161008002850064019612004520065200656128012820080028200160056200652006511160201100991001001600001000001011110119016200621600001002006620066200662006620066
1602042006515000000292580116100800161008002850064019612004520065200656128012820080028200160056200652006511160201100991001001600001000000011110119016200621600001002006620066200662006620066
1602042006515100000292580116100800161008002850064019612004520065200656128012820080028200160056200652006511160201100991001001600001000000011110119016200621600001002006620066200662006620066
1602042006515000000292580116100800161008002850064019612004520065200656128012820080028200160056200652006511160201100991001001600001000000011110119016200621600001002006620066200662006620066
1602042006515000000292580116100800161008002850064019612004520065200656128012820080028200160056200652006511160201100991001001600001000000011110119016200621600001002006620066200662006620066
1602042006515000000292580116100800161008002850064019612004520065200656128012820080028200160056200652006511160201100991001001600001000000011110119016200621600001002006620066200662006620066
1602042006515000000292580116100800161008002850064019612004520065200656128012820080028200160056200652006511160201100991001001600001000000011110119016200621600001002006620066200662006620066
1602042006515000000292580116100800161008002850064019612004520065200656128012820080028200160056200652006511160201100991001001600001000000011110119016200621600001002006620066200662006620066

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2506

retire uop (01)cycle (02)03mmu table walk data (08)1e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f6061696d6emap rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acc9cfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0eaec? simd retires (ee)? int retires (ef)f5f6f7f8fd
16002420093156012512580010108000010800005064000000020027200502005032280010200800002016000020046200501116002110910101600001000010049312242021221820047150160000102004720054200472004720047
160024200461550408452580010108000010800005064000011020027200462004632280010200800002016000020046200461116002110910101600001000010044811222021292120043150160000102004720047200472004720047
16002420046155032445258001010800001080000506400001102002720046200463228001020080000201600002004620046111600211091010160000100001003331192121120920043150160000102004720047200472004720047
160024200461561045258001010800001080000506400001002002720046200463228001020080000201600002004620046111600211091010160000100001004411522020412212120043150160000102004720051200472004720051
16002420046156035451258001010800001080000506400000052003120050200503228001020080000201600002005020051111600211091010160000100001003464292041292020043300160000102004720047200512004720051
16002420046155027945258001010800001080000506400000052003120046200503228001020080000201600002004620046111600211091010160000100001004782272022237720044150160000102004920051200472004720047
16002420046155039452580010108000010800005064000011520027200462004632280010200800002016000020046200461116002110910101600001000010043841202021117620043150160000102004720047200472004720047
1600242004615603964525800101080000108000050640000115200272004620046322800102008013620160000200462004611160021109101016000010000100458112020211202120043300160000102004720047200472004720047
1600242004616100512580010108000010800005064000011520027200502005032280010200800002016000020050200461116002110910101600001000010036661202021182020043150160000102004720047200472005120051
1600242004615601251258001010800001080000506400000052002720050200463228001020080000201600002004620046111600211091010160000100001004811222220411202120043150160000102004720047200472005120047

Test 5: throughput

Count: 16

Code:

  fcvtxn2 v0.4s, v16.2d
  fcvtxn2 v1.4s, v16.2d
  fcvtxn2 v2.4s, v16.2d
  fcvtxn2 v3.4s, v16.2d
  fcvtxn2 v4.4s, v16.2d
  fcvtxn2 v5.4s, v16.2d
  fcvtxn2 v6.4s, v16.2d
  fcvtxn2 v7.4s, v16.2d
  fcvtxn2 v8.4s, v16.2d
  fcvtxn2 v9.4s, v16.2d
  fcvtxn2 v10.4s, v16.2d
  fcvtxn2 v11.4s, v16.2d
  fcvtxn2 v12.4s, v16.2d
  fcvtxn2 v13.4s, v16.2d
  fcvtxn2 v14.4s, v16.2d
  fcvtxn2 v15.4s, v16.2d
  movi v16.16b, 17

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2502

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)1e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfl1i cache miss demand (d3)d5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
16020440058310000204251601081001600081001600205001280132040020400394003919977619990160120200160032200320064400394003911160201100991001001600001000000011110118001600400361600001004004040040400404004040040
16020440039311000156251601081001600081001600205001280132040020400394003919977619990160120200160032200320064400394003911160201100991001001600001000000011110118001600400361600001004004040040400404004040040
16020440039310000341251601081001600081001600205001280132040020400394003919977619990160120200160032200320064400394003911160201100991001001600001000000211110118001600400361600001004004040040400404004040040
16020440039310003602251601081001600081001600205001280132040020400394003919977619990160120200160032200320064400394003911160201100991001001600001000000011110118001600400361600001004004040040400404004040040
16020440039310000644251601081001600081001600205001280132040020400394003919977619990160120200160032200320064400394003911160201100991001001600001000000011110118001600400361600001004004040040400404004040040
1602044003931000030251601081001600081001600205001280132040020400394003919977619990160120200160032200320064400394003911160201100991001001600001000000011110118001600400361600001004004040040400404004040040
1602044003931000030251601081001600081001600205001280132040020400394003919977619990160120200160032200320064400394003911160201100991001001600001000000011110118001600400361600001004004040040400404004040040
1602044003931000030251601081001600081001600205001280132040020400394003919977619990160120200160032200320064400394003911160201100991001001600001000000011110118001600400361600001004004040040400404004040040
1602044003931000030251601081001600081001600205001280132040020400394003919977619990160120200160032200320064400394003911160201100991001001600001000000011110118001600400361600001004004040040400404004040040
1602044003931000030251601081001600081001600205001280132040020400394003919977619990160120200160032200320064400394003911160201100991001001600001000000011110118001600400361600001004004040040400404004040040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2502

retire uop (01)cycle (02)03l1i tlb fill (04)mmu table walk instruction (07)l2 tlb miss instruction (0a)0f1e3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)accfd0d2l1i cache miss demand (d3)l1i tlb miss demand (d4)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0? int output thing (e9)eaebec? simd retires (ee)? int retires (ef)f5f6f7f8fd
16002440039311001001174251600101016000010160000501280000104002040039400391999632001916001020160000203200004003940039111600211091010160000100000100223110461711131244003601650160000104004040040400404004040040
16002440039310000001499251600101016000010160000501280000114002040039400391999632001916001020160000203200004003940039111600211091010160000100000100223110311611122324003601650160000104004040040400404004040040
160024400393100010901902516001010160000101600005012800001140020400394003919996320019160010201600002032000040039400391116002110910101600001000001002462201916322322340036031100160000104004040040400404004040040
160024400393100100004282516001010160000101600005012800000140020400394003919996320019160010201600002032000040039400391116002110910101600001000031002531103316321323240036031100160000104004040040400404004040040
160024400393110000004262516001010160000101600005012800000140020400394003919996320019160010201600002032000040039400391116002110910101600001000061002462203216322313240036031100160000104004040040400404004040040
160024400393110010013832516001010160000101600005012800000040020400394003919996320019160010201600002032000040039400391116002110910101600001000001002462203116322213140036131100160000104004040040400404004040040
1600254057031000100012782516001010160000101600005012800000140020400394003919996320019160010201600002032000040039400391116002110910101600001000012100243110321611124314003602170160000104004040040400404004040040
160024400393111000121453251600101016000010160000501280000104002040039400391999632001916001020160000203200004003940039111600211091010160000100003100233111311611127324003602070160000104004040040400404004040040
16002440039311100001420251600101016000010160000501280000114002040039400391999632001916001020160000203200004003940039111600211091010160000100000100253111321611132324003602160160000104004040040400404004040040
16002440039310111000460251600101016000010160000501280000104002040039400391999632001916001020160000203200004003940039111600211091010160000100000100276221321621131254003602170160000104004040040400404004040040