Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FCVTXN (scalar, D)

Test 1: uops

Code:

  fcvtxn s0, d0
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
100430372306125472510001000100039816003018303730372414329141000100010003037303711100110000073116112629100030383038303830383038
10043037259010325472510001000100039816003018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
1004303723576125472510001000100039816003018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
10043037231806125472510001000100039816013018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
10043037231476125472510001000100039816013018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
100430372406125472510001000100039816003018303730372418328951000100010003037303711100110000073116112629100030383038303830383038
100430372206125472510001000100039816013018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
1004303722015625472510001000100039816013018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
100430372206125472510001000100039816013018303730372414328951000100010003037303711100110000073116112629100030383038303830383038
1004303723061254725100010001000398160030183037303724143289510001000100030373037111001100002173116112629100030383038303830383038

Test 2: Latency 1->2

Code:

  fcvtxn s0, d0
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)030e18191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0eb? simd retires (ee)? int retires (ef)f5f6f7f8fd
10204300372330001206129547251010010010000100100005004277160030018300373003728264328745101002001000020010000300373003711102011009910010010000100000071011611296420100001003003830038300383003830038
1020430037232000006129547251010010010000100100005004277160030018300373003728264328745101002001000020010000300373003711102011009910010010000100000071011611296330100001003003830038300383003830038
1020430037232800906129547251010010010000100100005004277160030018300373003728264328745101002001000020010000300373003711102011009910010010000100000071011611296333100001003003830038300383003830038
1020430037233000006129547251010010010000100100005004277160030018300373003728264328745101002001000020010000300373003711102011009910010010000100000071011611296330100001003003830038300383003830038
1020430037233000006129547251010010010000100100005004277160030018300373003728264328745101002001000020010000300373003711102011009910010010000100000071011611296330100001003003830038300383003830038
1020430037233000006129547251010010010000100100005004277160030018300373003728264328745101002001000020010000300373003711102011009910010010000100000071011611296330100001003003830038300383003830038
10204300372330000064129547251010010010000100100005004277160030018300373003728264328745101002001000020010000300373003711102011009910010010000100000071011611296330100001003003830038300383003830038
1020430037233000006129547251010010010000100100005004277160130018300373003728264328745101002001000020010000300373003711102011009910010010000100000071011611296330100001003003830038300383003830038
10204300372330000010329547251010010010000100100005004277160030018300373003728264328745101002001000020010000300373003711102011009910010010000100000071011611296330100001003003830038300383003830038
1020430037233000006129547251010010010000100100005004277160030018300373003728264328745101002001000020010000300373003711102011009910010010000100000071011611296330100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)acldst x64 uop (b1)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024300372331000021900656229547251001010100001010000504277160130018300373022628300328767100102010000201000030037301791110021109101010000100010006404165529629010000103008430038300383003830038
100243003723300100384006129547251001010100001010000504277160130018300373022628301328841100102210000201065330037300371110021109101010000100000006425165529629010000103003830038300383003830038
100243003723300000519006129547251001010100001010000504277160030018300373003728286328767100102010000201000030037300371110021109101010000100000006405165529629010000103007130038300383003830038
1002430037241000006150061329547441001010100241010000504277160130126300373003728286328767100102010000201000030037300371110021109101010000100000006405164429629010000103003830038300383003830038
1002430037233000000006129547251001010100001010000504277160130018300373003728286328767100102010000201000030037300371110021109101010000100000006406164429629010000103003830038300383003830038
100243003723200000408006129547251001010100001010000504277160030018300373003728286328767100102010000201000030037300371110021109101010000100000006405164629629010000103003830038300383003830038
100243003723300000483006129520601004513100562111650664293384130018300373003728286328767100102010652201000030037300371110021109101010000100200844006405525529629010000103003830038300383003830038
10024300372330000438126406129547251001010100001010000554277160030090300373003728298328767100102010657201000030037300371110021109101010000100000006405164529629010000103003830038300383003830038
10024300372330000000048929547251001010100001010000504277160030018300373003728286328767100102010000201000030037300371110021109101010000100000006404165529629010000103003830038300383003830038
100243003723300000513006129547251001010100001010000504277160130018300373003728286328767100102010000201000030037300371110021109101010000100000006405165629631010000103003830038300383003830038

Test 3: throughput

Count: 8

Code:

  fcvtxn s0, d8
  fcvtxn s1, d8
  fcvtxn s2, d8
  fcvtxn s3, d8
  fcvtxn s4, d8
  fcvtxn s5, d8
  fcvtxn s6, d8
  fcvtxn s7, d8
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk instruction (07)1e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)dde0? simd retires (ee)? int retires (ef)f5f6f7f8fd
8020420049155100302580108100800081008002050064013202002020039200399977699908012020080032200800322003920039118020110099100100800001004601115118116020036800001002004020040200402004020040
8020420039155000302580108100800081008002050064013202002020039200399977699908012020080032200800322003920039118020110099100100800001004561115118116020036800001002004020040200402004020040
80204200391560688302580108100800081008002050064013202002020039200399977699908012020080032200800322003920039118020110099100100800001002181115118016020036800001002004020040200402004020040
8020420039155000459258021210080008100801265006401320200202003920039997769990801202008003220080032200392003911802011009910010080000100001115118016020036800001002004020040200402004020040
802042003915500030258010810080008100800205006401320200202003920039997769990801202008003220080032200392003911802011009910010080000100001115118016020036800001002004020040200402004020040
802042003915500030258010810080008100800205006401320200202003920039997769990801202008003220080032200392003911802011009910010080000100001115118016020036800001002004020040200402004020040
8020420039155012030258010810080008100800205006401320200202003920039997769990801202008003220080032200392003911802011009910010080000100001115118016020036800001002004020040200402004020040
80204200391570003672580108100800081008002050064013202002020039200399977699908012020080032200800322003920039118020110099100100800001004231115118016020036800001002004020040200402004020040
8020420039156000229258010810080008100800205006401320200202003920039997769990801202008003220080032200392003911802011009910010080000100101115118016020036800001002004020040200402004020040
802042003915500030258010810080008100800205006401320200202003920039997769990801202008003220080032200392003911802011009910010080000100001115118016020036800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk instruction (07)mmu table walk data (08)1e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fst unit uop (a7)l1d cache writeback (a8)acbranch mispred nonspec (cb)cfd0d5map dispatch bubble (d6)daddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80024200501500004025800101080000108000050640000020020020039200399996310019800102080000208000020039200391180021109101080000100000502004160112003680000102004020040200402004020040
8002420039150011504025800101080000108000050640836020083020099200399996310019800102080000208000020039200391180021109101080000100000502001160112003680000102004020040200402004020040
80024200391500004025800101080000108000050640000020020020039200399996310019800102080000208000020039200391180021109101080000100000502001160112003680000102004020040200402004020040
80024200391500004025800101080000108000050640000020020020039200399996310019800102080000208000020039200391180021109101080000100000502001160112003680000102004020040200402004020040
80024200391500034025800101080000108000050640000020020020039200399996310019800102080000208000020039200391180021109101080000100000502001160112003680000102004020040200402004020040
80024200391500004025800101080000108000050640000020020020039200399996310019800102080000208000020039200391180021109101080000102101502001160112003680000102004020040200402004020040
800242003915000040258001010800001080000506400000200200200392003999963100198001020800002080000200392003911800211091010800001000150502001160112003680000102004020040200402004020040
80024200391500004025800101080000108000050640000020020020039200399996310019800102080000208000020039200391180021109101080000100090502001160112003680000102004020040201422004020040
800242003915000040258010610800001080000506400000200200200392003999963100198001020800002080000200392003911800211091010800001002690502001160112003680000102004020040200402004020040
800242003915000040258001010800001080000506400000200200200392003999963100198001020800002080000200392003911800211091010800001006530502001160112003680000102004020040200402004020040