Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FCVTZS (scalar, fixed-point, D to D)

Test 1: uops

Code:

  fcvtzs d0, d0, #3
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d tlb miss (a1)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)f5f6f7f8fd
1004303724061254725100010001000398160030183037303724143289510001000100030373037111001100000073116112629100030383038303830383038
1004303724061254725100010001000398160130183037303724143289510001000100030373037111001100000073116112629100030383038303830383038
1004303724061254725100010001000398160130183037303724143289510001000100030373037111001100000073116112629100030383038303830383038
1004303724061254725100010001000398160030183037303724143289510001000100030373037111001100000073116112642100030383038303830383038
1004303724061254725100010001000398160130183037303724143289510001000100030373037111001100000073116112629100030383038303830383038
1004303723061254725100010001000398160030183037303724143289510001000100030373037111001100000073116112629100030383038303830383038
1004303724061254725100010001000398160130183037303724143289510001000100030373037111001100000073116112629100030383038303830383038
1004303723061254725100010001000398160130183037303724143289510001000100030373037111001100000073116112629100030383038303830383038
1004303723082254725100010001000398160030183037303724143289510001000100030373037111001100000373116112629100030383038303830383038
1004303724084254725100010001000398160030183037303724143289510001000100030373037111001100000073116112629100030383038303830383038

Test 2: Latency 1->2

Code:

  fcvtzs d0, d0, #3
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)031e3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
102043003723327612954725101001001000010010000500427716003001830037300372826432874510100200100002001000030037300371110201100991001001000010000071011611296330100001003003830038300383003830038
10204300372320612954725101001001000010010000500427716003001830037300372826432874510100200100002001000030037300371110201100991001001000010000071011611296330100001003003830038300383003830038
1020430037232154612954725101001001000010010000500427716013001830037300372826432874510100200100002001000030037300371110201100991001001000010000071011611296330100001003003830038300383003830038
102043003723301032954725101001001000010010000500427716013001830180300372826432874510100200100002001000030037300371110201100991001001000010020371011611296330100001003003830038300383003830038
102043003723301032954725101001001000010010000500427716003001830037300372826432874510100200100002001000030037300371110201100991001001000010000071011611296330100001003003830038300383003830038
10204300372330612954725101001001000010010000500427716013001830037300372826432874510100200100002001000030037300371110201100991001001000010000071011611296330100001003003830038300383003830038
10204300372330612954725101001001000010010000500427716013001830037300372826432874510100200100002001000030037300371110201100991001001000010000071011611296330100001003003830038300383003830038
102043003723318612954725101001001000010010000500427716013012630037300372826432874510100200100002001000030037300371110201100991001001000010000071011611296330100001003003830038300383003830038
102043003723336612954725101001001000010010000500427716013001830037300372826432874510100200100002001000030037300371110201100991001001000010000071011611296330100001003003830038300383003830038
10204300372330612954725101001001000010010000500427716003001830037300372826432874510100200100002001000030037300371110201100991001001000010000071011611296330100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)6061696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cdcfd0d2d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024300372320000000612954725100101010000101000050427716000300183003730037282863287671001020100002010000300373003711100211091010100001000000000640002162229629010000103003830038300383003830038
10024300372330000000612954725100101010000101000050427716000300183003730037282863287671001020100002010000300373003711100211091010100001010000000640002162229629010000103003830038300383003830038
10024300372330000000612954725100101010000101000050427716000300183003730037282863287671001020100002010000300373003711100211091010100001000000288000640002162229629010000103003830038300383003830038
10024300372330000000612954725100101010000101000050427716000300183003730037282863287671001020100002010000300373003711100211091010100001000000000640002162229629010000103003830038300383003830038
10024300372330000000612954725100101010000101000050427716000300183003730037282863287671001020100002010000300373003711100211091010100001000000000640002162229629010000103003830038300383003830038
10024300372330000000612954725100101010000101000050427716000300183003730037282863287671001020100002010000300373003711100211091010100001000000000640002162229629010000103003830038300383003830038
10024300372320000000612954725100101010000101000050427716000300183003730037282863287671001020100002010000300373003711100211091010100001000000000640002162229629010000103003830038300383003830038
10024300372330000000612954725100101010000101000050427716000300183003730037282863287671061320100002010000300373003711100211091010100001000000000640002162229699010000103003830038300383003830038
10024300372330000000612954725100101010000101000050427716000300183003730037282863287671001020100002010000300373003711100211091010100001000000000640002162229629010000103003830038300383003830038
10024300372250000000612954725100101010000101000050427716000300183003730037282863287671001020100002010000300373003711100211091010100001000000000640002162229629010000103003830038300383003830038

Test 3: throughput

Count: 8

Code:

  fcvtzs d0, d8, #3
  fcvtzs d1, d8, #3
  fcvtzs d2, d8, #3
  fcvtzs d3, d8, #3
  fcvtzs d4, d8, #3
  fcvtzs d5, d8, #3
  fcvtzs d6, d8, #3
  fcvtzs d7, d8, #3
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)0318191e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80204200581550003025801081008000810080020500640132020020200392003999776999080120200800322008003220039200391180201100991001008000010000311151180160020036800001002004020040200402004020040
80204200391550003025801081008000810080020500640132020020200392003999776999080120200800322008003220039200391180201100991001008000010000011151180160020036800001002004020040200402004020040
80204200391550003025801081008000810080020500640132020020200392003999776999080120200800322008003220039200391180201100991001008000010000011151180160020036800001002004020040200402007620040
8020420039156002153625801081008000810080020500640132020020200392003999776999080120200800322008003220039200391180201100991001008000010000011151180160020036800001002004020040200402004020040
80204200391550003025801081008000810080020500640132020020200392003999776999080120200800322008003220039200391180201100991001008000010000011151180160020036800001002004020040200402004020040
80204200391550003025801081008000810080020500640132020020200392003999776999080120200800322008003220039200391180201100991001008000010000011151180160020036800001002004020040200402004020040
80204200391550004025801081008000810080020500640132020020200392003999776999080120200800322008003220077200391180201100991001008000010000011151180160020036800001002004020040200402004020040
80204200391550003025801081008000810080020500640132020020200392003999776999080120200800322008003220039200391180201100991001008000010000011151180160020036800001002004020040200402004020040
80204200391550003025801081008000810080020500640132020020200392003999776999080120200800322008003220039200391180201100991001008000010000011151180160020036800001002004020040200402004020040
80204200391550003025801081008000810080020500640132020020200392003999776999080120200800322008003220039200391180201100991001008000010000011151180160020086800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)abaccfd5map dispatch bubble (d6)dbddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
800242003915564025800101080000108000050640000120020200392003999963100198001020800002080000200392003911800211091010800001000050206160222003680000102004020040200402004020040
800242003915504025800101080000108000050640000120020200392003999963100198001020800002080000200392003911800211091010800001000050203160262003680000102004020040200402004020040
8002420039155244025800101080000108000050640000120020200392003999963100198001020800002080000200392003911800211091010800001000050202160222003680000102004020040200402004020040
800242003915604025800101080000108000050640000120020200392003999963100198001020800002080000200392003911800211091010800001000350202160222003680000102004020040200402004020040
8002420039155040258001010800001080000506400001200202003920039100053100198001020801042080000200392003911800211091010800001000050206160362003680000102004020040200402004020040
8002420039155032525800101080000108000050640000120020200392003999963100198001020800002080000200392003911800211091010800001000050202160222003680000102004020040200402009020040
8002420039155364025800101080000108000050640000120020200392003999963100198001020800002080000200392003911800211091010800001000050202160662003680000102004020040200402004020040
800242003915504025800101080000108000050640000120020200392003999963100198001020800002080000200392003911800211091010800001000050202160622003680000102004020040200402004020040
8002420039155154025800101080000108000050640000120020200392003999963100198001020800002080000200392003911800211091010800001000050202160632003680000102004020040200402004020040
8002420039155082258001010800001080000506400001200202024120039999631001980010208000020800002003920039118002110910108000010015050202160222003680000102004020040200402004020040