Apple M1 Microarchitecture Research by Dougall Johnson

Firestorm: Overview | Base Instructions | SIMD and FP Instructions
Icestorm:  Overview | Base Instructions | SIMD and FP Instructions

FCVTZS (scalar, fixed-point, D to W)

Test 1: uops

Code:

  fcvtzs w0, d0, #3
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 3.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 2.000

retire (01)cycle (02)031e3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch fp/simd (57)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op fp/simd (7e)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst integer (97)a8accfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
2004541404325300010002000200018000052254154124832742000200020005415411110011000007311611538100010001000542542542542542
2004541404325300010002000200018000052254154124832742000200020005415411110011000007311611538100010001000542542542542542
2004541404325300010002000200018000052254154124832742000200020005415411110011000007311611538100010001000542542542542542
2004541404325300010002000200018000052254154124832742000200020005415411110011000007311611538100010001000542542542542542
2004541404325300010002000200018000052254154124832742000200020005415411110011000007311611538100010001000542542542542542
2004541504325300010002000200018000052254154124832742000200020005415411110011000007311611538100010001000542542542542542
2004541404325300010002000200018000052254154124832742000200020005415411110011000007311611538100010001000542542542542542
2004541404325300010002000200018000052254154124832742000200020005415411110011000107311611538100010001000542542542542542
2004541404325300010002000200018000052254154124832742000200020005415411110011000007311611538100010001000542542542542542
2004541404325300010002000200018000052254154124832742000200020005415411110011000007311611538100010001000542542542542542

Test 2: Latency 1->2 roundtrip

Code:

  fcvtzs w0, d0, #3
  fmov d0, x0
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 13.0038

retire (01)cycle (02)030b1e1f3f4f51inst issue (52)~issue int (53)~issue fp/simd (54)~issue ld/st (55)~dispatch int (56)~dispatch fp/simd (57)~dispatch ld/st (58)huge thing int (59)huge thing ld/st (5a)huge thing fp/simd (5b)60696b6d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op ld/st (7d)~map op fp/simd (7e)~map lookup int (7f)~map lookup ld/st (80)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa6a8acc2c5cdcfd0d5d6ddinst fetch restart (de)e0? int output thing (e9)ld/st retires (ed)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
30204130038100803013002611941725401001010020000100001002000010000500621497914801034013001301300381300381254763126246301002001000020000200100002000013003813003811202011009910010100100001001000000000131012162212952510000100001000010100130039130039130156130040130039
30204130038100800013002311941725401001010020000100001002000010000500621497914801034013001301300381300381254763126246301002001000020000200100002000013003813003811202011009910010100100001001000000000131012162212952510000100001000010100130039130039130039130039130039
30204130038100800013002311941725401001010020000100001002000010000500621497914801034013001301300381300381254763126246301002001000020000200100002000013003813003811202011009910010100100001001000000000131011162212952510000100001000010100130039130039130039130039130039
30204130074100809013002311942125401001010020000100001002000010000500621497914801034013001301300381300381254763126246301002001000020000200100002000013003813003811202011009910010100100001001000000000131012163212952510000100001000010100130039130039130039130039130039
30204130038100800013002311941725401001010020000100001002000010000500621497914801034013001301300381300381254763126246302672001000020000200100002000013003813003811202011009910010100100001001000000000131012162212952510000100001000010100130039130039130039130039130039
302041300381008018013012811941725401001010020000100001002000010000500621497914816073013001401300391300381254763126246301002001000020000200100002000013003813003811202011009910010100100001001000000000131012162212952510000100001000010100130039130039130039130039130039
30204130038974117721613002311941725401001010020000100001002000010000500621502714801258013001301300381300381254763126246301002001000020000200100002000013003813003811202011009910010100100001001000010000138312162212952810000100001000010100130039130039130039130039130039
3020413003897400013002311941725401001010020000100001002000010000500621497914801034113001301300381300381254773126246301002001000020000200100002000013003813003811202011009910010100100001001000000000131012162212952510000100001000010100130039130039130039130039130039
3020413003897400013002311941725401001010020000100001002000010000500621497914801034113001301300381300381254763126246301002001000020000200100002012913003813003811202011009910010100100001001000003000131012162212952510000100001000010100130039130039130039130039130073
3020413003897400013002311942725401001010020004100001002000010000500621497914801034013001301300381300381254763126246301002001000020000200100002000013003813003811202021009910010100100001001000000000131012162212952510000100001000010100130039130039130039130039130039

1000 unrolls and 10 iterations

Result (median cycles for code): 13.0038

retire (01)cycle (02)03080b18191e1f3a3f4f51inst issue (52)~issue int (53)~issue fp/simd (54)~issue ld/st (55)~dispatch int (56)~dispatch fp/simd (57)~dispatch ld/st (58)huge thing int (59)huge thing ld/st (5a)huge thing fp/simd (5b)60696b6d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op ld/st (7d)~map op fp/simd (7e)~map lookup int (7f)~map lookup ld/st (80)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa0a6a8a9acc2c5cfd5d6ddinst fetch restart (de)e0? int output thing (e9)ld/st retires (ed)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
3002413003897400005400130023119417254001010010200001000010201161000050621497914800025113001301300381300381255373126268300102010000200002010000204811300391300381120021109101001010000100100001030012702161112952510000100001000010010130039130039130039130039130039
300241300389740000000130023119417254001010010200001000010200001000050621497914800025113001301300381300381254983126303300102010000200002010000200001300381300381120021109101001010000100100000000012704162312952510000100001000010010130039130039130039130039130039
3002413003997400001200130023119417254001010010200001000010200001000050621497914800025113001301300381300381254983126313300102010000200002010000200001300381300381120021109101001010000100100000000012704161112952510000100001000010010130039130039130039130044130039
3002413003897600000001300231194182540010100172000010000102000010000506214979148000250130013013004013003812549828126274300102010000200002010000200001300421301221120021109101001010000100100004000012701161112952510000100001000010010130039130039130039130039130039
3002413003897400000001300261194171094001010010200001000010200001000050622470314800025113001301300381300381254983126268300102010000200002010000200001300381300405120021109101001010000100100000000012701161112952510000100001000010010130373130039130039130039130374
300241300389740000000130023119418254001010010200001000010200001000050621497914800025113023301300381300381254983126268300102210000200002010000200001300381300381120021109101001010000100100100000012701161112979810000100001000010010130039130039130039130039130039
30024130038974000094500130023119417254001010010200001000010200001000050621507514800025113001301300381300381254983126271300102010000200002010000200001300381300381120021109101001010000104100000030012701161112952510000100001000010010130039130039130039130040130039
300241300389740000300130023119417254001010010200001000010200001000050621497914800025113001301300381300381254983126268300102010000200002010000200001300381300381120021109101001010000100100004000012701161112952510000100001000010010130039130041130039130039130039
300241300389770000102900130025119417254003410010200001000010200001000050621507514811133113001301300381300381254983126268300102010000200002010000204901300381300381120021109101001010000100100002000012701162112952510000100001000010010130039130039130039130039130039
300241300389740000000130023119417254001010010200001000010200001000050621497914800025113001301300381300381254983126268300102010000200002010000200001300381300381120021109101001010000100100001000012701161112952510000100001000010010130039130039130039130043130039

Test 3: throughput

Count: 8

Code:

  fcvtzs w0, d8, #3
  fcvtzs w1, d8, #3
  fcvtzs w2, d8, #3
  fcvtzs w3, d8, #3
  fcvtzs w4, d8, #3
  fcvtzs w5, d8, #3
  fcvtzs w6, d8, #3
  fcvtzs w7, d8, #3
  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

retire (01)cycle (02)03090f1e3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)9fa7a8acc5branch mispredict (cb)cdcfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
1602044006531000090825240104801001600041001600205001440132040022400414004119977619992160120200160032200160032400414004111802011009910080100100020111511711600400388000080000801004004240042400424004240042
1602044004131000032252401048010016000410016002050014401320400224004140041199776199921601202001600322001600324004140041118020110099100801001000280111511701600400388000080000801004004240042400424004240042
1602044004131000032252401048010016000410016002050014401321400224004140041199776199921601202001600322001600324004140041118020110099100801001000620111511701600400388000080000801004004240042400424004240042
160204400413100003225240104801001600041001600205001440132140022400414004119977619992160120200160032200160032400414004111802011009910080100100023111511701600401058000080000801004004240042400424004240042
160204400413100003225240104801001600041001600205001440132040022400414004119977619992160120200160032200160032400414004111802011009910080100100030111511701600400388000080000801004004240042400424004240042
1602044004131000069725240104801001600041001600205001440132040022400414004119977619992160120200160032200160032400414004111802011009910080100100010111511701600400388000080000801004004240042400424004240042
1602044004131000032252401048010016000410016002050014401321400224004140041199776199921601202001600322001600324004140041118020110099100801001000280111511701600400388000080000801004004240042400424004240042
160204400413100003225240104801001600041001600205001440132040022400414004119977619992160120200160032200160032400414004111802011009910080100100006111511701600400388000080000801004004240042400424004240042
160204400413100003225240104801001600041001600205001440132140022400414004119977619992160120200160032200160032400414004111802011009910080100100026111511701600400388000080000801004004240042400424004240042
160204400413100003225240104801001600041001600205001440132040022400414004119977619992160120200160032200160032400414004111802011009910080100100020111511701600400388000080000801004004240042400424004240042

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

retire (01)cycle (02)030818191e1f3a3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696d6edispatch stall (70)74scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)9fa0a6a8a9accfd0d5d6ddinst fetch restart (de)e0? int output thing (e9)eaec? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
1600244005531000000084252400108001016000010160000501440000040022400414004119996032002116001020160000201600004004140041118002110910800101000000502001161140038800000080000800104004240042400424004240042
1600244004131100000042252400108001016000010160000501440000040022400414004119996032002116001020160000201600004004140041118002110910800101000000502001161140038800000080000800104004240042400424004240042
16002440041310000000707252400108001016000010160000501440000040022400414004119996032002116001020160000201600004004140041118002110910800101000000502001161140038800000080000800104004240042400424004240042
160024400413100040004225240010800101600001016000050144000004002240041400411999603200211600102016000020160000400414004111800211091080010100000246502001161140038800000080000800104004240042400424004240042
1600244004131000000042252400108001016000010160000501440000040022400414004119996032002116001020160000201600004004140041118002110910800101000100502001161140038800000080000800104004240042400424004240042
1600244004131000000042252400108001016000010160000501440000140022400414004119996032002116001020160000201600004004140041118002110910800101000000502001161140038800000080000800104004240042400424004240042
1600244004131100000042252400108001016000010160000501440000040022400414004119996032002116001020160000201600004004140041118002110910800101000000502001161140038800000080000800104004240042400424004240042
16002440041310000132004225240010800101600001016000050144000014002240041400411999603200211600102016000020160000400414004111800211091080010100000237502001161140038800000080000800104004240042400424004240042
160024400413100000006225240010800101600001016000050144000014002240041400411999603200211600102016000020160000400414004111800211091080010100000222502001161140038800000080000800104004240042400424004240042
1600244004131000051004225240010800101600001016000050144000004002240041400411999603200211600102016000020160000400414004111800211091080010100000207502001161140038800000080000800104004240042400424004240042