Firestorm: FCVTZS (scalar, fixed-point, D to X) measurements

Code:

  fcvtzs x0, d0, #3

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 3.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 2.000

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	19	1e	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch simd uop (57)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map simd uop (7e)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst int alu (97)	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
2004	541	4	0	0	43	25	3000	1000	2000	2000	18000	1	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	2	0	0	73	2	16	1	1	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	0	43	25	3000	1000	2000	2000	18000	1	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	1	0	0	73	1	16	1	1	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	0	43	25	3000	1000	2000	2000	18000	1	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	0	0	0	73	1	16	1	1	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	0	43	25	3000	1000	2000	2000	18000	0	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	0	0	0	73	1	16	1	1	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	0	43	25	3000	1000	2000	2000	18000	0	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	0	0	0	73	1	16	1	1	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	0	43	25	3000	1000	2000	2000	18000	0	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	0	0	0	73	1	16	1	1	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	0	43	25	3000	1000	2000	2000	18000	0	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	0	0	0	73	1	16	1	1	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	0	43	25	3000	1000	2000	2000	18000	0	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	1	0	0	73	1	16	1	1	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	0	138	25	3000	1000	2000	2000	18000	0	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	0	0	0	73	1	16	1	1	538	1000	1000	1000	542	542	542	542	542
2004	541	4	0	0	43	25	3000	1000	2000	2000	18000	0	522	541	541	248	3	274	2000	2000	2000	541	541	1	1	1001	1000	0	0	0	0	0	73	1	16	1	1	538	1000	1000	1000	542	542	542	542	542

Test 2: Latency 1->2 roundtrip

Code:

  fcvtzs x0, d0, #3
  fmov d0, x0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 13.0038

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	cd	cf	d0	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30204	130038	974	0	0	0	0	0	0	0	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6224272	14801034	1	130013	130038	130038	125629	3	126395	30100	202	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	0	1310	1	2	16	2	2	129525	10000	10000	10000	10100	130039	130089	130045	130041	130039
30204	130038	974	0	0	0	0	0	0	0	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	1	130013	130367	130042	125476	3	126246	30100	200	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	0	1310	1	4	16	4	2	129525	10000	10000	10000	10100	130090	130075	130369	130039	130039
30204	130038	974	0	0	0	0	0	0	0	0	130023	119420	106	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	1	130013	130038	130038	125477	3	126246	30100	200	10000	20000	200	10000	20000	130039	130041	5	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	0	1310	1	2	16	2	2	129525	10000	10000	10000	10100	130039	130106	130069	130042	130039
30204	130038	974	0	0	0	0	4	0	0	0	130023	119433	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14821753	1	130219	130038	130039	125482	6	126246	30771	200	10000	20000	200	10000	20000	130392	130040	1	1	20201	100	99	100	10100	10000	100	12	10000	0	0	3	0	0	1310	1	2	16	2	2	129525	10000	10000	10000	10100	130039	130090	130079	130040	130039
30204	130039	974	0	0	0	0	0	39	0	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	1	130013	130038	130038	125476	3	126246	30100	200	10000	20000	200	10000	20000	130283	130041	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	2	0	1310	1	3	16	2	2	129525	10000	10000	10000	10100	130039	130114	130056	130041	130039
30204	130039	974	0	0	0	0	0	459	0	0	130337	119417	25	40100	10100	20000	10000	100	20000	10000	500	6223886	14801034	1	130013	130038	130038	125480	3	126446	30100	200	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	2	10000	0	0	12	0	0	1310	1	2	16	2	2	129812	10000	10000	10000	10100	130039	130076	130051	130039	130039
30204	130038	974	0	0	0	0	0	0	0	0	130027	119417	25	40100	10100	20000	10000	100	20000	10196	500	6214979	14801034	1	130013	130038	130038	125631	3	126246	30100	200	10000	20000	200	10243	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	0	1310	1	2	16	2	2	129529	10000	10000	10000	10100	130039	130077	130067	130041	130039
30204	130038	974	0	0	0	0	0	0	0	0	130023	119420	109	40100	10100	20000	10000	100	20000	10000	500	6224317	14801034	0	130013	130038	130038	125476	3	126246	30100	200	10246	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	10000	1	0	0	0	0	1310	1	2	16	2	2	129733	10000	10000	10000	10100	130039	130085	130078	130045	130039
30204	130039	974	0	0	0	0	0	21	264	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	0	130013	130038	130038	125476	3	126246	30100	200	10000	20000	200	10000	20000	130038	130038	1	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	0	1310	1	2	16	2	2	129525	10000	10000	10000	10100	130039	130085	130727	130040	130039
30204	130038	974	0	0	0	0	0	0	0	0	130023	119417	25	40100	10100	20000	10000	100	20000	10000	500	6214979	14801034	0	130013	130038	130038	125476	3	126246	30100	200	10000	20000	200	10000	20000	130039	130041	5	1	20201	100	99	100	10100	10000	100	0	10000	0	0	0	0	0	1310	1	2	16	2	2	129525	10000	10000	10000	10100	130086	130089	130044	130039	130039

1000 unrolls and 10 iterations

Result (median cycles for code): 13.0038

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l2 tlb miss data (0b)	1e	1f	3f	4f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	60	69	6b	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	inst simd alu (9a)	9f	l1d tlb access (a0)	ld unit uop (a6)	l1d cache writeback (a8)	ac	cf	d5	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
30024	130489	978	0	0	0	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	0	130013	0	130038	130038	125498	3	126333	30010	20	10000	20000	20	10000	20000	130047	130039	1	1	20022	10	9	10	10010	10000	10	0	10000	1	0	1270	1	16	3	4	129537	10000	10000	10000	10010	130039	130039	130039	130039	130039
30024	130038	974	0	0	0	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	0	130013	0	130038	130038	125498	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	0	10003	0	0	1270	1	16	1	2	129528	10000	10000	10000	10010	130039	130039	130039	130039	130039
30024	130038	974	0	0	0	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	0	130013	0	130038	130038	125498	3	126311	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	1270	1	16	1	3	129527	10000	10000	10000	10010	130040	130039	130040	130039	130039
30024	130038	974	0	0	112	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	0	130013	0	130038	130038	125498	3	126270	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	2	10000	0	0	1270	1	16	1	3	129556	10000	10000	10000	10010	130039	130039	130039	130039	130039
30024	130040	1028	0	48	0	130187	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	0	130014	0	130038	130038	125498	3	126268	30010	20	10000	20131	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	1270	1	16	1	3	129525	10000	10000	10000	10010	130039	130039	130039	130039	130042
30024	130038	974	0	0	0	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	0	130013	0	130038	130038	125498	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	1270	2	16	1	1	129527	10000	10000	10000	10010	130039	130039	130039	130039	130039
30024	130038	973	0	0	0	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	0	130017	0	130038	130038	125498	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	1270	1	16	1	3	129525	10000	10000	10000	10010	130039	130039	130039	130039	130039
30024	130038	974	0	0	0	130023	119423	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	0	130013	0	130038	130038	125498	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	1270	1	16	1	3	129526	10000	10000	10000	10010	130039	130039	130039	130039	130039
30024	130038	974	0	0	0	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	0	130013	0	130038	130038	125498	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	2	1	20021	10	9	10	10010	10000	10	0	10000	0	0	1270	1	16	2	2	129525	10000	10000	10000	10010	130039	130039	130039	130039	130039
30024	130038	974	0	0	0	130023	119417	25	40010	10010	20000	10000	10	20000	10000	50	6214979	14800025	0	130013	0	130038	130038	125498	3	126268	30010	20	10000	20000	20	10000	20000	130038	130038	1	1	20021	10	9	10	10010	10000	10	0	10000	0	0	1270	1	16	1	1	129552	10000	10000	10000	10010	130039	130039	130039	130039	130039

Test 3: throughput

Count: 8

Code:

  fcvtzs x0, d8, #3
  fcvtzs x1, d8, #3
  fcvtzs x2, d8, #3
  fcvtzs x3, d8, #3
  fcvtzs x4, d8, #3
  fcvtzs x5, d8, #3
  fcvtzs x6, d8, #3
  fcvtzs x7, d8, #3

Initialization

  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	mmu table walk data (08)	09	l2 tlb miss data (0b)	18	19	1e	1f	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	rob full (74)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb access (a0)	l1d tlb miss (a1)	ld unit uop (a6)	l1d cache writeback (a8)	a9	ac	c2	branch cond mispred nonspec (c5)	branch mispred nonspec (cb)	cd	cf	map dispatch bubble (d6)	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160204	40041	300	0	0	0	0	0	0	0	32	25	240338	80100	160004	100	160020	500	1440132	1	40022	40041	40041	19977	0	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	0	1	0	0	0	1	1	1	5181	16	0	0	40038	80000	80000	80100	40042	40042	40042	40042	40042
160204	40041	299	0	0	0	0	0	21	0	222	25	240104	80100	160196	100	160020	500	1440132	1	40022	40041	40041	19977	0	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	1	1	1	5117	16	0	0	40038	80000	80000	80100	40042	40042	40042	40042	40042
160204	40041	299	0	0	0	0	0	0	0	32	25	240104	80100	160004	100	160020	500	1440132	1	40068	40041	40041	19977	0	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	1	1	1	5117	16	0	0	40038	80000	80000	80100	40042	40042	40042	40042	40042
160204	40041	299	0	0	0	0	0	0	0	32	25	240104	80100	160004	100	160020	500	1440132	1	40022	40041	40041	19977	0	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	1	1	1	5117	16	0	0	40038	80000	80000	80100	40042	40042	40042	40042	40042
160204	40041	300	0	0	0	0	0	0	0	32	25	240104	80100	160004	100	160020	500	1441756	0	40022	40041	40041	19977	0	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	0	2	0	3	0	1	1	1	5117	16	0	0	40038	80000	80000	80100	40042	40042	40042	40042	40042
160204	40041	300	0	0	0	3	1	132	0	2543	341	243602	81248	162156	102	162508	572	1462042	1	40728	40916	40914	20259	0	100	20576	162592	204	162510	204	161924	40988	40921	13	1	80201	100	99	100	80100	100	0	2	0	0	0	7555	0	1	1	1	5117	16	0	0	40038	80294	80000	80100	40682	40681	40835	40765	40762
160204	40839	305	0	0	0	10	11	810	988	2492	163	243476	81438	162556	104	162460	600	1461790	1	40852	40986	40995	20262	0	97	20587	162746	202	162512	204	162478	40992	41072	14	1	80201	100	99	100	80100	100	2	0	0	1	0	8138	0	1	1	1	5117	16	0	0	40038	80000	80000	80100	40042	40042	40042	40042	40042
160204	40041	300	0	0	1	0	0	0	0	32	25	240104	80100	160004	100	160020	635	1445836	0	40662	40830	40924	20171	0	93	20494	162770	204	160856	200	162280	41161	40992	12	1	80201	100	99	100	80100	100	0	0	2	0	4	3753	0	1	1	1	5117	25	0	0	40038	80000	80000	80100	40042	40042	40042	40042	40042
160204	40041	300	0	0	0	0	0	0	0	74	25	240104	80100	160004	100	160020	500	1440132	1	40022	40041	40041	19977	0	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	1	1	1	5117	16	1	0	40038	80000	80000	80100	40042	40042	40042	40042	40042
160204	40041	299	0	0	0	0	0	0	0	53	25	240104	80100	160004	100	160020	500	1440132	1	40083	40041	40041	19977	0	6	19992	160120	200	160032	200	160032	40041	40041	1	1	80201	100	99	100	80100	100	0	0	0	0	0	0	0	1	1	1	5117	16	0	0	40038	80000	80000	80100	40042	40042	40042	40042	40042

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

All non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	03	l1i tlb fill (04)	mmu table walk instruction (07)	l2 tlb miss data (0b)	18	19	1e	1f	3a	3f	51	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	ldst uops in schedulers (5b)	60	69	6d	6e	map stall dispatch (70)	map rewind (75)	map stall (76)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	82	83	flush restart other nonspec (84)	85	inst all (8c)	inst branch (8d)	inst branch taken (90)	inst branch cond (94)	inst int alu (97)	9f	l1d tlb miss (a1)	l1d cache writeback (a8)	ac	cf	d0	l1i tlb miss demand (d4)	d5	map dispatch bubble (d6)	db	dd	fetch restart (de)	e0	? int output thing (e9)	? simd retires (ee)	? int retires (ef)	f5	f6	f7	f8	fd
160024	40054	311	1	0	0	0	0	0	0	0	42	25	240010	80010	160000	10	160000	0	50	1440000	0	40022	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	0	5020	0	0	24	16	0	23	22	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	310	0	0	0	0	0	0	0	0	42	25	240010	80010	160000	10	160000	0	50	1440000	0	40022	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	0	5020	0	0	26	16	0	21	25	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	310	0	0	0	0	0	0	0	0	42	25	240010	80010	160000	10	160000	0	50	1440000	0	40022	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	0	5020	0	0	24	16	0	24	20	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	311	0	0	0	0	0	0	0	0	42	25	240010	80010	160000	10	160000	0	50	1440000	0	40022	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	0	5020	0	0	14	16	0	22	26	40038	80000	80000	80010	40042	40042	40125	40043	40042
160024	40041	379	0	0	0	0	0	99	152	0	760	25	240010	80010	160000	10	160000	0	50	1440000	1	40022	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	0	5020	0	0	27	16	0	16	33	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	310	0	0	0	0	0	0	0	0	42	25	240010	80010	160000	10	160000	0	50	1440000	1	40022	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	0	5020	0	0	29	16	0	28	28	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	311	0	0	0	0	0	0	0	0	42	25	240010	80010	160000	10	160000	0	50	1440000	1	40022	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	0	5020	0	0	25	16	0	26	27	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	310	0	0	0	0	0	0	0	0	42	25	240010	80010	160000	10	160000	0	50	1440000	1	40022	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	0	5020	0	0	27	16	0	20	28	40038	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	322	0	0	0	0	0	54	0	0	707	25	240010	80010	160000	10	160000	0	50	1440000	1	40022	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	0	5020	0	0	17	16	0	28	31	40294	80000	80000	80010	40042	40042	40042	40042	40042
160024	40041	310	0	0	0	0	0	0	0	0	126	25	240010	80010	160000	10	160000	0	50	1440000	0	40022	40041	40041	19996	3	20021	160010	20	160000	20	160000	40041	40041	1	1	80021	10	9	10	80010	10	0	0	0	5020	0	0	27	16	0	34	34	40038	80000	80000	80010	40042	40042	40042	40042	40042

FCVTZS (scalar, fixed-point, D to X)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations