Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FCVTZS (scalar, fixed-point, D to X)

Test 1: uops

Code:

  fcvtzs x0, d0, #3
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 3.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 2.000

retire uop (01)cycle (02)03191e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst int alu (97)l1d tlb access (a0)ld unit uop (a6)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
20045414004325300010002000200018000152254154124832742000200020005415411110011000002007321611538100010001000542542542542542
20045414004325300010002000200018000152254154124832742000200020005415411110011000001007311611538100010001000542542542542542
20045414004325300010002000200018000152254154124832742000200020005415411110011000000007311611538100010001000542542542542542
20045414004325300010002000200018000052254154124832742000200020005415411110011000000007311611538100010001000542542542542542
20045414004325300010002000200018000052254154124832742000200020005415411110011000000007311611538100010001000542542542542542
20045414004325300010002000200018000052254154124832742000200020005415411110011000000007311611538100010001000542542542542542
20045414004325300010002000200018000052254154124832742000200020005415411110011000000007311611538100010001000542542542542542
20045414004325300010002000200018000052254154124832742000200020005415411110011000001007311611538100010001000542542542542542
200454140013825300010002000200018000052254154124832742000200020005415411110011000000007311611538100010001000542542542542542
20045414004325300010002000200018000052254154124832742000200020005415411110011000000007311611538100010001000542542542542542

Test 2: Latency 1->2 roundtrip

Code:

  fcvtzs x0, d0, #3
  fmov d0, x0
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 13.0038

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)18191e1f3a3f4f51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cdcfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
302041300389740000000013002311941725401001010020000100001002000010000500622427214801034113001313003813003812562931263953010020210000200002001000020000130038130038112020110099100101001000010001000000000131012162212952510000100001000010100130039130089130045130041130039
302041300389740000000013002311941725401001010020000100001002000010000500621497914801034113001313036713004212547631262463010020010000200002001000020000130038130038112020110099100101001000010001000000000131014164212952510000100001000010100130090130075130369130039130039
3020413003897400000000130023119420106401001010020000100001002000010000500621497914801034113001313003813003812547731262463010020010000200002001000020000130039130041512020110099100101001000010001000000000131012162212952510000100001000010100130039130106130069130042130039
3020413003897400004000130023119433254010010100200001000010020000100005006214979148217531130219130038130039125482612624630771200100002000020010000200001303921300401120201100991001010010000100121000000300131012162212952510000100001000010100130039130090130079130040130039
3020413003997400000390013002311941725401001010020000100001002000010000500621497914801034113001313003813003812547631262463010020010000200002001000020000130283130041112020110099100101001000010001000000020131013162212952510000100001000010100130039130114130056130041130039
302041300399740000045900130337119417254010010100200001000010020000100005006223886148010341130013130038130038125480312644630100200100002000020010000200001300381300381120201100991001010010000100210000001200131012162212981210000100001000010100130039130076130051130039130039
302041300389740000000013002711941725401001010020000100001002000010196500621497914801034113001313003813003812563131262463010020010000200002001024320000130038130038112020110099100101001000010001000000000131012162212952910000100001000010100130039130077130067130041130039
3020413003897400000000130023119420109401001010020000100001002000010000500622431714801034013001313003813003812547631262463010020010246200002001000020000130038130038112020110099100101001000010001000010000131012162212973310000100001000010100130039130085130078130045130039
302041300399740000021264013002311941725401001010020000100001002000010000500621497914801034013001313003813003812547631262463010020010000200002001000020000130038130038112020110099100101001000010001000000000131012162212952510000100001000010100130039130085130727130040130039
302041300389740000000013002311941725401001010020000100001002000010000500621497914801034013001313003813003812547631262463010020010000200002001000020000130039130041512020110099100101001000010001000000000131012162212952510000100001000010100130086130089130044130039130039

1000 unrolls and 10 iterations

Result (median cycles for code): 13.0038

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e1f3f4f51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
30024130489978000130023119417254001010010200001000010200001000050621497914800025013001301300381300381254983126333300102010000200002010000200001300471300391120022109101001010000100100001012701163412953710000100001000010010130039130039130039130039130039
30024130038974000130023119417254001010010200001000010200001000050621497914800025013001301300381300381254983126268300102010000200002010000200001300381300381120021109101001010000100100030012701161212952810000100001000010010130039130039130039130039130039
30024130038974000130023119417254001010010200001000010200001000050621497914800025013001301300381300381254983126311300102010000200002010000200001300381300381120021109101001010000100100000012701161312952710000100001000010010130040130039130040130039130039
3002413003897400112130023119417254001010010200001000010200001000050621497914800025013001301300381300381254983126270300102010000200002010000200001300381300381120021109101001010000102100000012701161312955610000100001000010010130039130039130039130039130039
3002413004010280480130187119417254001010010200001000010200001000050621497914800025013001401300381300381254983126268300102010000201312010000200001300381300381120021109101001010000100100000012701161312952510000100001000010010130039130039130039130039130042
30024130038974000130023119417254001010010200001000010200001000050621497914800025013001301300381300381254983126268300102010000200002010000200001300381300381120021109101001010000100100000012702161112952710000100001000010010130039130039130039130039130039
30024130038973000130023119417254001010010200001000010200001000050621497914800025013001701300381300381254983126268300102010000200002010000200001300381300381120021109101001010000100100000012701161312952510000100001000010010130039130039130039130039130039
30024130038974000130023119423254001010010200001000010200001000050621497914800025013001301300381300381254983126268300102010000200002010000200001300381300381120021109101001010000100100000012701161312952610000100001000010010130039130039130039130039130039
30024130038974000130023119417254001010010200001000010200001000050621497914800025013001301300381300381254983126268300102010000200002010000200001300381300382120021109101001010000100100000012701162212952510000100001000010010130039130039130039130039130039
30024130038974000130023119417254001010010200001000010200001000050621497914800025013001301300381300381254983126268300102010000200002010000200001300381300381120021109101001010000100100000012701161112955210000100001000010010130039130039130039130039130039

Test 3: throughput

Count: 8

Code:

  fcvtzs x0, d8, #3
  fcvtzs x1, d8, #3
  fcvtzs x2, d8, #3
  fcvtzs x3, d8, #3
  fcvtzs x4, d8, #3
  fcvtzs x5, d8, #3
  fcvtzs x6, d8, #3
  fcvtzs x7, d8, #3
  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)18191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)rob full (74)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfmap dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
16020440041300000000032252403388010016000410016002050014401321400224004140041199770619992160120200160032200160032400414004111802011009910080100100000100011151811600400388000080000801004004240042400424004240042
1602044004129900000210222252401048010016019610016002050014401321400224004140041199770619992160120200160032200160032400414004111802011009910080100100000000011151171600400388000080000801004004240042400424004240042
16020440041299000000032252401048010016000410016002050014401321400684004140041199770619992160120200160032200160032400414004111802011009910080100100000000011151171600400388000080000801004004240042400424004240042
16020440041299000000032252401048010016000410016002050014401321400224004140041199770619992160120200160032200160032400414004111802011009910080100100000000011151171600400388000080000801004004240042400424004240042
16020440041300000000032252401048010016000410016002050014417560400224004140041199770619992160120200160032200160032400414004111802011009910080100100000203011151171600400388000080000801004004240042400424004240042
1602044004130000031132025433412436028124816215610216250857214620421407284091640914202590100205761625922041625102041619244098840921131802011009910080100100020007555011151171600400388029480000801004068240681408354076540762
1602044083930500010118109882492163243476814381625561041624606001461790140852409864099520262097205871627462021625122041624784099241072141802011009910080100100200108138011151171600400388000080000801004004240042400424004240042
1602044004130000100003225240104801001600041001600206351445836040662408304092420171093204941627702041608562001622804116140992121802011009910080100100002043753011151172500400388000080000801004004240042400424004240042
16020440041300000000074252401048010016000410016002050014401321400224004140041199770619992160120200160032200160032400414004111802011009910080100100000000011151171610400388000080000801004004240042400424004240042
16020440041299000000053252401048010016000410016002050014401321400834004140041199770619992160120200160032200160032400414004111802011009910080100100000000011151171600400388000080000801004004240042400424004240042

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

retire uop (01)cycle (02)03l1i tlb fill (04)mmu table walk instruction (07)l2 tlb miss data (0b)18191e1f3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb miss (a1)l1d cache writeback (a8)accfd0l1i tlb miss demand (d4)d5map dispatch bubble (d6)dbddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1600244005431110000000422524001080010160000101600000501440000040022400414004119996320021160010201600002016000040041400411180021109108001010000502000241602322400388000080000800104004240042400424004240042
1600244004131000000000422524001080010160000101600000501440000040022400414004119996320021160010201600002016000040041400411180021109108001010000502000261602125400388000080000800104004240042400424004240042
1600244004131000000000422524001080010160000101600000501440000040022400414004119996320021160010201600002016000040041400411180021109108001010000502000241602420400388000080000800104004240042400424004240042
1600244004131100000000422524001080010160000101600000501440000040022400414004119996320021160010201600002016000040041400411180021109108001010000502000141602226400388000080000800104004240042401254004340042
16002440041379000009915207602524001080010160000101600000501440000140022400414004119996320021160010201600002016000040041400411180021109108001010000502000271601633400388000080000800104004240042400424004240042
1600244004131000000000422524001080010160000101600000501440000140022400414004119996320021160010201600002016000040041400411180021109108001010000502000291602828400388000080000800104004240042400424004240042
1600244004131100000000422524001080010160000101600000501440000140022400414004119996320021160010201600002016000040041400411180021109108001010000502000251602627400388000080000800104004240042400424004240042
1600244004131000000000422524001080010160000101600000501440000140022400414004119996320021160010201600002016000040041400411180021109108001010000502000271602028400388000080000800104004240042400424004240042
160024400413220000054007072524001080010160000101600000501440000140022400414004119996320021160010201600002016000040041400411180021109108001010000502000171602831402948000080000800104004240042400424004240042
16002440041310000000001262524001080010160000101600000501440000040022400414004119996320021160010201600002016000040041400411180021109108001010000502000271603434400388000080000800104004240042400424004240042