Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FCVTZS (scalar, fixed-point, H to W)

Test 1: uops

Code:

  fcvtzs w0, h0, #3
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 3.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 2.000

retire uop (01)cycle (02)031e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst int alu (97)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
200454140432530001000200020001800005225415412483274200020002000541541111001100007321622538100010001000542542542542542
200454140432530001000200020001800005225415412483274200020002000541541111001100007321622538100010001000542542542542542
200454140432530001000200020001800005225415412483274200020002000541541111001100007321622538100010001000542542542542542
200454140432530001000200020001800005225415412483274200020002000541541111001100007321622538100010001000542542542542542
200454140432530001000200020001800005225415412483274200020002000541541111001100007321622538100010001000542542542542542
200454140852530001000200020001800005225415412483274200020002000541541111001100007321622538100010001000542542542542542
200454140432530001000200020001800015225415412483274200020002000541541111001100007321622538100010001000542542542542542
200454140432530001000200020001800015225415412483274200020002000541541111001100007321622538100010001000542542542542542
200454140432530001000200020001800005225415412483274200020002000541541111001100007321622538100010001000542542542542542
2004541401222530001000200020001800005225415412483274200020002000541541111001100007321622538100010001000542542542542542

Test 2: Latency 1->2 roundtrip

Code:

  fcvtzs w0, h0, #3
  fmov d0, x0
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 13.0038

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3a3f4f51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)ea? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
30204130038974000000013002311941725401001010020000100001002000010000500621497914801034013001301300381300381254836126242301002001000220006200100022000613003813003811202011009910010100100001000010000000601111317011611129534100000100001000010100130130130039130039130039130039
3020413003897400000001300231194172540100101002000010000100200001000050062149791480103401300130130038130038125483612624230100200100022000620010002200061300381300381120201100991001010010000100001000000013201111317021612129533100000100001000010100130039130039130039130039130039
302041300389740000000130023119417254010010100200001000010020000100005006214979148010340130013013003813003812548361262423010020010002200062001000220006130038130038112020110099100101001000010000100000008701111318011621129533100000100001000010100130039130039130039130039130039
30204130040974000000013002311941725401001010020000100001002000010000500621497914801034013001301300381300381254836126242301002001000220006200100022000613003813003811202011009910010100100001000010000000601111317011611129533100000100001000010100130039130039130039130039130039
3020413003997400000001300231194172540100101002000010000100200001000050062149791480103401300133130039130038125483612624130100200100022000620010000200001300381300381120202100991001010010000100001000000018600001310121622129525100000100001000010100130039130039130039130039130039
30204130371975000000113072511942025401001010020000100001002000010000500621497914801034113001301300381300381254763126249301002001000020000200100002000013004513003811202011009910010100100001000010000000900001310121622129525100000100001000010100130039130039130039130039130039
302041300579740000000130023119417254010010100200001000010020000100005006214979148010341130013013003813003812547631262463010020010000200002001000020000130038130038112020110099100101001000010000100000001200011310121622129525100000100001000010100130039130039130039130039130039
30204130038974000000013002311943125401001010020000100001002000010000500621497914801034013001301300381300381254763126247301002001000020000200100002000013003813003811202011009910010100100001000010000000600001310121622129525100000100001000010100130039130039130039130039130039
30204130062974000000013002311941725401001010020000100001002000010000500621497914801034013001301300381300381254763126246301002001000020000200100672000013004113003811202011009910010100100001000010000000900001310121622129525100000100001000010100130039130039130039130039130039
302041300409740000000130023119417254010010100200001000010020000100005006214979148010341130013013003813003812547631262463010020010000200002001000020000130038130038112020110099100101001000010000100000001500001310121622129525100000100001000010100130039130039130039130039130039

1000 unrolls and 10 iterations

Result (median cycles for code): 13.0038

retire uop (01)cycle (02)0318191e1f3f4f51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)accfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
30024130038974000013002311941725400101001020000100001020000100005062149791480002501300130130038130110125498312626830010201000020000201000020000130038130038112002110910100101000010100000012702162112952510000100001000010010130039130039130039130039130039
30024130038974000013005511941725400101001020000100001020000100005062150751480002501300130130038130091125498312626830010201000020000201000020131130038130038112002110910100101000010100000012701161112952510000100001000010010130039130039130039130039130039
30024130038974000013002311941725400101001020000100001020000100005062149791480002501300133130038130080125503312626830010201000020000201000020000130038130038112002110910100101000010100000012701161112952510000100001000010010130039130039130039130039130039
30025130040974010013002311941725400101001020002100001020000100005062149791480002501300130130119130041125498312626830010201000020000201000020000130038130038112002110910100101000010100000012701161112952510000100001000010010130039130039130039130039130039
30024130038974000013002311941725400101001020000100001020000100005062149791480002501300130130038130111125498312626830010201000020000201000020000130038130038112002110910100101000010100005012701161112952510000100001000010010130039130039130039130039130039
30024130038974000013002311941725400101001020000100001020000100005062149791480002501300130130038130090125498312626830010201000020000201000020000130038130038112002110910100101000010100000012701161112952510000100001000010010130039130039130039130039130039
30024130038974000013002311941725400101001020000100001020000100005062149791480002501300130130118130081125498312626930010201000020000201000020000130038130038112002110910100101000010100000012701162112952510000100001000010010130039130039130039130069130039
30024130038974000013002311941725400101001020000100001020000100005062149791480002501300130130122130043125498312626830010201000020000201000020000130038130038112002110910100101000010100000012701161112952510000100001000010010130039130039130039130039130039
30024130038974000013002311941725400101001020000100001020000100005062149791480002501300130130081130040125498312626830010201000020000201000020000130038130038112002110910100101000010100000012701161112952510000100001000010010130039130039130039130039130039
30024130038974000013002311941725400101001020000100001020000100005062149791480002501300130130038130122125498312626830010201000020000201000020000130038130038112002110910100101000010100000012701161112952510000100001000010010130039130039130039130039130039

Test 3: throughput

Count: 8

Code:

  fcvtzs w0, h8, #3
  fcvtzs w1, h8, #3
  fcvtzs w2, h8, #3
  fcvtzs w3, h8, #3
  fcvtzs w4, h8, #3
  fcvtzs w5, h8, #3
  fcvtzs w6, h8, #3
  fcvtzs w7, h8, #3
  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)0f18191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd store (99)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)a9acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)daddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
160204400663110000000032252401048010016000410016002050014401321400220400414004119977619992160120200160032200160032400414004111802011009910080100010000000001115117416000400388000080000801004004240042400424004240042
16020440041311000000003225240104801001600041001602205001440132040022040041400411997761999216031220016003220016003240041400411180201100991008010001002030007351115135034000401058000080000801004004240042400424004240042
16020440041310000000017632252404028010016000410016002052014401320402170400414004119977619992160120200160032200160032400414004111802011009910080100010000000001115117016000400388000080000801004004240042400424004240042
160204400413110000000095252401048010016000410016002050014401320400220400414004119977619992160120200160032200160032400414004111802011009910080100010000000001115117016000400388000080000801004004240042400424004240042
1602044004132200000000542252401048010016000410016002050014401320400220400414004119977619992160120200160032200160032400414004111802011009910080100010000000001115117016000401918000080000801004004240042400424012240042
16020440041311001000003071712401048029816000410016002050014401320400220400414004119977619992160120200160032200160032400414004111802011009910080100010000001031115117016000400388000080000801004004240042400424004240042
1602044004131100000000179252401048010016000410016002050014401320400220400414004119977619992160120200160032200160032400414004111802011009910080100010000001001115117016000400388000080000801004004240042400424004240042
160204400413100000000032252401048010016000410016002050014401320400220400414004119977619992160120200160032200160032400414004111802011009910080100010000001001115117016000400388000080000801004004240042400424004240042
160204400413100000000032252401048010016000410016002050014401321400220400414004119977619992160120200160032200160032400414004111802011009910080100010000000091115117016000400388000080000801004004240042400424004240042
160204400413100000000032252401048010016000410016002050014401321400220400414004119977619992160120200160032200160032400414004111802011009910080100010000000001115117016000400388000080000801004004240042400424004240042

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

retire uop (01)cycle (02)03mmu table walk instruction (07)1e1f3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)accfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9daddfetch restart (de)e0? int output thing (e9)ea? simd retires (ee)? int retires (ef)f5f6f7f8fd
16002440042310000063252400108001016000010160000501440000014002240041400411999632002116001020160000201600004004140041118002110910800101000502000014160012284003880000080000800104004240042400424004240042
16002440041322000018412524001080010160000101600005014400001140022400414004119996192002116001020160000201600004004140041118002110910800101000502000015160014144003880000080000800104004240042400424004240042
1600244004131100001359252400108001016000010160000501440000014002240041400411999632002116001020160000201600004004140041118002110910800101000502000011160014104003880000080000800104004240042400424004240042
1600244004131000001174252400108001016000010160000501440000014002240041400411999632002116001020160000201600004004140041118002110910800101000502000013160013174003880000080000800104004240042400424004240042
1600244004131000001189252400108001016000010160000501440000114002240041400411999632002116001020160000201600004004140041118002110910800101000502000013160015164003880000080000800104004240042400424004240042
1600244004131100001704252400108001016000010160000501440000014002240041400411999632002116001020160000201600004004140041118002110910800101000502000016160016134003880000080000800104004240042400424004240042
160024400413100000337252400108001016000010160000501440000014002240041400411999632002116001020160000201600004004140041118002110910800101000502000013160017144003880000080000800104004240042400424004240042
160024400413100000393252400108001016000010160000501440000014002240041400411999632002116001020160000201600004004140041118002110910800101000502000016160016134003880000080000800104004240042400424004240042
1600244004131100001264252400108001016000010160000501440000014002240041400411999632002116001020160000201600004004140041118002110910800101010502000013160015184003880000080000800104004240042400424004240042
160024400413760005378252400108001016000010160000501440000014002240041400411999632002116001020160000201600004004140041118002110910800101010502000010160017134003880000080000800104004240042400424004240042