Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FCVTZS (scalar, fixed-point, H to X)

Test 1: uops

Code:

  fcvtzs x0, h0, #3
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 3.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 2.000

retire uop (01)cycle (02)03mmu table walk data (08)09l2 tlb miss data (0b)18191e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst int alu (97)l1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
2004541400000043253000100020002000180000522541541248327420002000200054154111100110000000007311611538100010001000542542542542542
2004541500000064253000100020002000180000522541541248327420002000200054154111100110000000007311611538100010001000542542542542542
2004541400000043253000100020002000180001522541541248327420002000200054154111100110000000007311611538100010001000542542542542542
2004541400000043253000100020002000180001522541541248327420002000200054154111100110000000007311611538100010001000542542542542542
2004541400000043253000100020002000180000522541541248327420002000200054154111100110000000007311611538100010001000542542542542542
2004541400000043253000100020002000180001522541541248327420002000200054154111100110000000007311611538100010001000542542542542542
2004541400000043253000100020002000180000522541541248327420002000200054154111100110000000007311611538100010001000542542542542542
2004541400000943253000100020002000180000522541541248327420002000200054154111100110000000007311611538100010001000542542542542542
20045414000001243253000100020002000180000522541541248327420002000200054154111100110000000007311611538100010001000542542542542542
2004541400000043253000100020002000180000522541541248327420002000200054154111100110000000307311611538100010001000542542542542542

Test 2: Latency 1->2 roundtrip

Code:

  fcvtzs x0, h0, #3
  fmov d0, x0
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 13.0038

retire uop (01)cycle (02)030918191e3f4f51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)a9acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
30204130038974000013002711941725401001010020000100001002000010000500621497914801034013001313003813003812547631262463010020010000200002001000020000130038130038112020110099100101001000010010000000000131012162212957110000100001000010100130043130039130039130039130039
30204130038974000013002311941725401001010020000100001002000010000500621497914801034013001313003813003812547631262463010020010000200002001000020000130038130038112020110099100101001000010010000000000132812163212992410004100001000010100130039130039130039130039130383
30204130038975000013002311941725401001010020000100001002000010000500621497914801034013001313003813003812547631262463010020010000200002001006420000130038130038112020110099100101001000010010000000000131012162212952510000100001000010100130044130039130039130039130039
30204130038974000013002411941725401001010020000100001002000010000500621497914801034013001313003813003812547631262463010020010000200002001000020000130038130124112020110099100101001000010010000000000131012162212952510013100001000010100130039130039130039130039130039
30204130038974000013002311941725401001010020000100001002000010000500621497914801034013001313004113003812547631262463010020010000200002001000020000130038130038112020110099100101001000010010000000000131012162212952510000100001000010100130039130039130039130039130039
30204130039974000013002311941725401001010020000100001002000010000500621497914801034013001313003813003812547631262463010020010000200002001000020000130038130038112020110099100101001000010010000400000131012173212960910000100001000010100130039130039130039130039130039
30204130038974000013002311942025401001010020000100001002000010000500621497914801034013001313003813003812547631262463010020010000200002001000020000130038130038112020110099100101001000010010000000000131012162212952510000100001000010100130039130039130039130039130039
30204130038974000013002311942325401001010020000100001002000010000500621507514801034013001313003813003812547631262463010020010000200002001000020000130038130038112020110099100101001000010010000000000131012162212952510000100001000010100130039130039130039130039130039
30204130038974100013002311941725401001010020000100001002000010000500621497914801034013001313003813003812547631262463010020010000200002001000020000130038130039112020210099100101001000010010000000000131012162212952510000100001000010100130039130039130039130039130039
30204130038974000013002311941725401001010020000100001002000010000500621497914801034013001313003813003812547631262463010020010000200002001000020000130038130038112020110099100101001000010010000000000131012162212952510000100001000010100130077130086130039130039130039

1000 unrolls and 10 iterations

Result (median cycles for code): 13.0038

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)18191e1f3f4f51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)5f60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)l1d cache writeback (a8)a9acc2branch mispred nonspec (cb)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
30024130038100800002010130023119417254001010010200001000010200001000050621497914800025001300131300381300381255403126268300102010000200002010000200001300381300381120021109101001010000100100000000012702161112952510000100001000010010130039130039130039130039130039
300241300381008000000130023119417254001010010200001000010200001000050621497914800025011300131300381300571255133126268300102010000200002010000200001300381300381120021109101001010000100100000030012701162112952510000100001000010010130039130039130039130039130039
30024130038974000000130023119417254001010010200001000010200001000050621497914800025011300131300381300381254993126268300102010000200002010000200001300381300381120021109101001010000100100000000112701161112952910000100001000010010130039130039130039130039130039
30024130038974000000130023119417254001010010200001000010200001000050621497914800025011300131300381301091254993126268300102010000200002010066200001300381300412120021109101001010000100100000000012701161112967510000100001000010010130039130039130040130041130039
30024130038974000000130023119417254001010010200001000010200001000050621497914800025011300131300381300381255103126268300102010124200002010000200001300381300381120021109101001010000100100000000012701162112952510000100001000010010130039130039130039130039130039
30024130038973000000130023119417254001010010200001000010200001000050621497914800025011300131300381300961254983126268300102010000200002010000200001300381300381120021109101001010000100100000000012701161112952510000100001000010010130039130039130039130039130039
30024130038974000000130023119417254001010010200001000010200001000050621497914800025011300131300481300961254983126268301742010000200002010000201311300381300381120021109101001010000100100000000012701161112952510000100001000010010130039130039130039130039130039
30024130038974000000130023119417254001010010200001000010200001000050621497914800025011300131300381300981255003126268300102010000200002010000200001300381300381120021109101001010000100100000000012701161112952510000100001000010010130042130042130039130039130039
30024130038974000000130023119417254001010010200001000010200001000050621497914800025011300131300871300381254983126268300102010000200002010000200001300381300381120021109101001010000100100000000012704161112952510000100001000010010130039130039130039130039130039
30024130038974000000130023119417254001010010200001000010200001000050621497914800025001300131300911300611254983126268300102010000201312010065200001300701300411120021109101001010000100100000000012703161112952510000100001000010010130039130039130039130039130039

Test 3: throughput

Count: 8

Code:

  fcvtzs x0, h8, #3
  fcvtzs x1, h8, #3
  fcvtzs x2, h8, #3
  fcvtzs x3, h8, #3
  fcvtzs x4, h8, #3
  fcvtzs x5, h8, #3
  fcvtzs x6, h8, #3
  fcvtzs x7, h8, #3
  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

retire uop (01)cycle (02)0318191e1f3a3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)st unit uop (a7)l1d cache writeback (a8)acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
160204400413000000032252401048010016000410016002050014401320400224004140041199776199921601202001600322001600324004140041118020110099100801001000000000111511701600400388000080000801004004240042400424004240042
16020440041311000006162252401048010016000410016002050014401320400224004140041199776199921601202001600322001600324004140041118020110099100801001000000030111511701600400388000080000801004004240042400424004240042
16020440041299000001022252401048010016000410016002050014419890400224004140041199776199921601202001600322001600324004140041118020110099100801001000000030111511701600400388000080000801004004240042400424004240042
16020440041300009264032252401048010016000410016002050014401320400224004140041199776199921601202001600322001600324004140041118020110099100801001002000000111511701600400388000080000801004004240042400424004240042
1602044004130000390032252401048010016000410016002050014401320400224004140041199776199921601202001600322001600324004140041118020110099100801001000000000111511701600400388000080000801004004240042400424004240042
16020440041300001500825252401048010016000410016002050014401320400224004140041199776199921601202001600322001600324004140041118020110099100801001000000000111511711600400388000080000801004004240042400424004240042
160204400412990000032252401048010016000410016002050014401320400224004140041199776199921601202001600322001600324004140041118020110099100801001000000000111511701600400388000080000801004004240042400424004240042
160204400413000000074252401048010016000410016002050014401320400224004140041199776199921601202001600322001600324004140041118020110099100801001000000000111511701600400388000080000801004004240042400424004240042
160204400413020000032252401048010016000410016002050014401320402764004140041199776199921603122001600322001600324004140041118020110099100801001000000000111511701600400388010080000801004004240042400424004240123
160204401983020000032252401048010016000410016002050014401320400224004140041199776199921601202001600322001600324004140041118020110099100801001000020100111511701600400388000080000801004004240042400424004240042

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

retire uop (01)cycle (02)03l2 tlb miss instruction (0a)1e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)acc2cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)eb? simd retires (ee)? int retires (ef)f5f6f7f8fd
16002440054300045422524001080010160000101600005014400000400224004140041199963200211600102016000020160000400414004111800211091080010100005020116114003880000080000800104004240042400424004240042
16002440041300021422524001080010160000101600005014400000400224004140041199963200211600102016000020160000400414004111800211091080010100005020116114003880000080000800104004240042400424004240042
160024400413000213422524001080010160000101600005014400000400224004140041199963200211600102016000020160000400414004111800211091080010100025020116114003880000080000800104004240042400424004240042
16002440041301027422524001080010160000101600005014400000400224004140041199963200211600102016000020160000400414004111800211091080010100005020116114003880000080000800104004240042400424004240042
16002440041300012422524001080010160000101600005014400000400224004140041199963200211600102016000020160000400414004111800211091080010100005020116114003880000080000800104004240042400424004240042
1600244004130003422524001080010160000101600005014400000400224004140041199963200211600102016000020160000400414004111800211091080010100005020116114003880000080000800104004240042400424004240042
160024400413000261422524001080010160000101600005014400000400224004140041199963200211600102016000020160000400414004111800211091080010100005020116114003880000080000800104004240042400424004240042
16002440041300051422524001080010160000101600005014400000400224004140041199963200211600102016000020160000400414004111800211091080010100005020116114003880000080000800104004240042400424004240042
16002440041300012422524001080010160000101600005014400000400224004140041199963200211600102016000020160000400414004111800211091080010100005020116114003880000080000800104004240042400424004240042
16002440041300063422524001080010160000101600005014400000400224004140041199963200211600102016000020160000400414004111800211091080010100005020116114003880000080000800104004240042400424004240042