Apple M1 Microarchitecture Research by Dougall Johnson

Firestorm: Overview | Base Instructions | SIMD and FP Instructions
Icestorm:  Overview | Base Instructions | SIMD and FP Instructions

FCVTZS (scalar, fixed-point, S to X)

Test 1: uops

Code:

  fcvtzs x0, s0, #3
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 3.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 2.000

retire (01)cycle (02)03080b181e1f3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch fp/simd (57)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op fp/simd (7e)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst integer (97)a0a7a8a9acc2cfd5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
200454140000043253000100020002000180001522541541248327420002000200054154111100110000000007321622538100010001000542542542542542
200454140009085253000100020002000180001522541541248327420002000200054154111100110000020007321622538100010001000542542542542542
200454140000043253000100020002000180000522541541248327420002000200054154111100110000000007321622538100010001000542542542542542
200454140000043253000100020002000180001522541541248327420002000200054154111100110000000007321622538100010001000542542542542542
200454140000043253000100020002000180000522541541248327420002000200054154111100110000000007321622538100010001000542542542542542
200454140006043253000100020002000180000522541541248327420002000200054154111100110000030007321622538100010001000542542542542542
200454140000064253000100020002000180001522541541248327420002000200054154111100110000000007321622538100010001000542542542542542
200454140000043253000100020002000180001522541541248327420002000200054154111100110000000007321622538100010001000542542542542542
200454140000043253000100020002000180000522541541248327420002000200054154111100110000000007321622538100010001000542542542542542
200454140000043253000100020002000180000522541541248327420002000200054154111100110000000007321622538100010001000542542542542542

Test 2: Latency 1->2 roundtrip

Code:

  fcvtzs x0, s0, #3
  fmov d0, x0
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 13.0038

retire (01)cycle (02)0307080a0b18191e1f3a3f4f51inst issue (52)~issue int (53)~issue fp/simd (54)~issue ld/st (55)~dispatch int (56)~dispatch fp/simd (57)~dispatch ld/st (58)huge thing int (59)huge thing ld/st (5a)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op ld/st (7d)~map op fp/simd (7e)~map lookup int (7f)~map lookup ld/st (80)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa1a6a8a9acc2c5branch mispredict (cb)cdcfd0d5d6ddinst fetch restart (de)e0? int output thing (e9)ld/st retires (ed)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
302041300389740000000001300231194172540100101002000010000100200001000050062149791480103411300131300381300381254836126242301002001000220006200100022000613003813003811202011009910010100100001000100000000111131803161212959510000100001000010100130039130042130039130040130039
302041300389741010000001301031194172540127101002000010000100200001000050062149791480103411300131300381300381254836126242301002001000220006200100022000613003813003811202011009910010100100001000100000000000131014163312952510000100001000010100130039130039130039130039130039
302041300389740000009001300231194172540100101002000010000100200001000050062149791480103401300131300381300381254763126246301002001000020000200100002000013003813003811202021009910010100100001000100001030000131013163412952510000100001000010100130039130039130039130039130039
3020413003897400000000013002311941725401001010020000100001002000010000500621497914801034113001313003813003812547620126246301002001000020000200100002000013003813003811202011009910010100100001000100000000010131013164412952510000100001000010100130039130039130039130039130039
302041300389740000000001300231194172540100101002000010000100200001000050062149791480103411300131300381300381254813126246304382001000020000200100002000013003813003811202011009910010100100001000100000000000131014163312952610000100001000010100130039130071130040130039130121
302041302169740201240001300231194172540100101002000010000100200001000050062149791480103411300131300381300381254763126246301002001000020000200100002000013003813003811202011009910010100100001000100001030000131014163312952910000100001000010100130372130456130117130039130042
302041300389740000000001300231194172540100101002000010000100200001000050062149791480103411300131300381300381254763126246301002001000020000200100002000013003813003811202011009910010100100001000100000000000131013163312952510000100001000010100130039130039130039130039130039
302041300389740000000001300231194172540100101002000010000100200001000050062149791480103411300131300381300381254763126246301002001000020000200100002000013003813003811202011009910010100100001000100000000000131013163412952510000100001000010100130039130039130039130039130039
302041300389740000000001300231194172540100101002000010000100200001000050062149791480205901300131300381300381254763126246301002001000020000200100002000013003813003811202011009910010100100001000100000000000131013163312952510000100001000010100130039130039130039130039130039
302041300389740000003001300231194172540100101002000010000100200001000050062149791480103411300131300381300381254763126246301002001000020000200100002000013003813003811202011009910010100100001000100000000000131013163412952510000100001000010100130039130039130039130039130039

1000 unrolls and 10 iterations

Result (median cycles for code): 13.0038

retire (01)cycle (02)03080b18191e1f3f4f51inst issue (52)~issue int (53)~issue fp/simd (54)~issue ld/st (55)~dispatch int (56)~dispatch fp/simd (57)~dispatch ld/st (58)huge thing int (59)huge thing ld/st (5a)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op ld/st (7d)~map op fp/simd (7e)~map lookup int (7f)~map lookup ld/st (80)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)inst neon or fp (9a)9fa0a1a6a8a9acc2c5cdcfd5d6ddinst fetch restart (de)e0? int output thing (e9)ld/st retires (ed)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
3002413005397601104501300231194172540010100102000010000102000010000506222416148001391130085130040130038125499312627030010201000020000201000020000130038130038112002110910100101000010021000000000012706165112957510000100001000010010130039130039130039130040130039
30024130038974100100130023119419254001010010200001000010200001004950621497914800025113001313006813003812549820512790634642221073422425241024720000130038130038112002110910100101000010001000012000013431162112953010000100001000010010130039130039130039130039130039
300241300389740000001300231194172540010100102000010000102000010000506214979148000251130013130038130038125498312626830010201000020000201000020000130038130038112002110910100101000010001000000000012701161112954610000100001000010010130039130039130039130333130042
300241300389740000001300231194172540010100102000010000102000010000506215027148000251130013130038130038125502312646830010201000020000201000020000130038130382212002110910100101000010001000000000012701161112952510000100001000010010130039130039130039130039130039
300241300389740000001300231194172540010100102000010007102000010000506214979148000251130013130076130038125498312626830010201000020000201000020000130038130038212002110910100101000010001000042000012701161112952910000100001000010010130040130039130357130041130039
300241300389740000513521300231194172540034100102000010000112000010000616215075148000251130013130038130040125498312626830010201000020000201000020000130038130038112002110910100101000010021000000000012701161112952510000100001000010010130042130382130039130039130039
3002413003897400001201300591194222540010100102000010000102000010000506214979148000251130013130038130038125498312626830010201000020000201000020000130038130038512002110910100101000010021000062000012701482212952510000100001000010010130039130039130039130376130041
3002413003897400000013002311942025400101001020000100001020000100005062149791480002511300131300381300381254982712626830010201000020000201000020000130038130038112002110910100101000010001000010000012701161112952510000100001000010010130039130042130386130039130039
300241300389740000001300231194172540010100102000010000102000010000506214979148000251130013130038130038125498312626830010201000020000201024720000130038130038112002110910100101000010001000000000012701161112952510000100001000010010130039130039130039130039130039
300241300389740000001300231194202540010100102000010000102000010000506214979148000251130013130038130038125498312626830010201000020000201024320000130038130038112002110910100101000010001000000000012701161112952510000100001000010010130039130039130039130039130039

Test 3: throughput

Count: 8

Code:

  fcvtzs x0, s8, #3
  fcvtzs x1, s8, #3
  fcvtzs x2, s8, #3
  fcvtzs x3, s8, #3
  fcvtzs x4, s8, #3
  fcvtzs x5, s8, #3
  fcvtzs x6, s8, #3
  fcvtzs x7, s8, #3
  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

retire (01)cycle (02)0304080b0e18191e1f3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)6061696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)9fa8acc5branch mispredict (cb)cdcfd0d5d6ddinst fetch restart (de)e0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
160204400723000000000032252401048010016000410016002050014401321040022400414004119977619992160120200160032200160032400414004111802011009910080100100001115117001600400388000080000801004004240042400424004240042
1602044004130000000000697252401048010016000410016002050014401320040022400414004120003619992160120200160032200160032400414004111802011009910080100100101115117001600400388000080000801004004240042400424004240042
160204400413000000000032252401048010016000410016002050014401321040022400414004119977619992160120200160032200160032400414004111802011009910080100100001115117011600400388000080000801004004240042403614004240042
160204400413000000000032252401048010016000410016002050014401321040022400414004119977619992160120200160032200160032400414004111802011009910080100100001115117001600400388000080000801004004240042400424004240042
160204400413000000000032252401048010016000410016002050014401321040022400414004119977619992160120200160032200160032400414004111802011009910080100100031115117001600400388000080000801004004240042400424004240042
160204400413000000000032252401048010016000410016002050014401320040022400414004119977619992160120200160032200160032400414004111802011009910080100100001115117001600400388000080000801004004240042400424004240042
1602044004130000000000424252401048010016000410016002050014401320040083400414004119977619992160120200160032200160032400414004111802011009910080100100001115117001600400388000080000801004004240042400424004240042
160204400413000000000032252401048010016000410016002050014401320040022400414004119977619992160120200160032200160032400414004111802011009910080100100001115117001600400388000080000801004004240368400424004240042
160204400413000000000032252401048010016000410016002050014401320040022400414004119977619992160120200160032200160032400414004111802011009910080100100001115117001600400388000080000801004004240042400424004240204
160204401173011110010032752406948028616039610016002050014401321040022400414004119977619992160120200160032200160032400414012231802011009910080100100001115117001602401688000080000801004004240042400424004240123

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

retire (01)cycle (02)031e3f51inst issue (52)~issue int (53)~issue fp/simd (54)~dispatch int (56)~dispatch fp/simd (57)huge thing int (59)huge thing fp/simd (5b)60696d6edispatch stall (70)scheduler rewind (75)scheduler stall (76)~dispatch op (78)~map op int (7c)~map op fp/simd (7e)~map lookup int (7f)~map lookup fp/simd (81)8283pipeline redirect (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst b.cc (94)inst integer (97)9fa8a9acbranch mispredict (cb)cfd0d5d6d9ddinst fetch restart (de)dfe0? int output thing (e9)? fp/simd (ee)gpr retires (ef)f5f6f7f8fd
160024400552990422524001080010160000101600005014400000400224004140041199963200211600102016000020160000400414004111800211091080010103000502331160113400388000080000800104004240042400424004240042
16002440041300042252400108001016060410160000501440000140022400414004119996122006616001020160822201600004004140041118002110910800101041000502331160113400388000080000800104004240109400424004240042
1600244004129994225240010800101600001016000050144000014002240041400411999632002116001020160000201600004004140041118002110910800101043000502331160113400388000080000800104004240042400424004240042
1600244004130004225240010800101600001016000050144000004002240041400411999632002116001020160000201600004004140041118002110910800101059000502331160113400388000080000800104004240042400424004240042
1600244004129904225240010800101600001016000050144000014002240041400411999632002116001020160000201600004004140041118002110910800101027000502331160113400388000080000800104004240042400424004240042
1600244004130004225240010800101600001016000050144000014002240041400411999632002116001020160000201600004004140041118002110910800101056000502331160113400388000080000800104004240042400424004240042
1600244004130004225240010800101607901016000050144000004002240041400411999632002116001020160000201600004004140041118002110910800101037000502331160113400388000080000800104004240042400424004240042
1600244004130004225240010800101600001016000050144000004002240041400411999632002116001020160000201600004004140041118002110910800101040000502331160113400388000080000800104004240042400424004240042
1600244004130004225240010800101600001016000050144000004002240041400411999632002116001020160000201600004004140041118002110910800101010060502331160113400388000080000800104004240042400424004240042
1600244004131004225240010800101600001016000050144000014002240041400411999632002116001020160000201600004004140041118002110910800101055000502331160113400388000080000800104004240042400424004240042