Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FCVTZS (scalar, integer, D to D)

Test 1: uops

Code:

  fcvtzs d0, d0
  movi v0.16b, 1
  movi v1.16b, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 1.000

retire uop (01)cycle (02)0309l2 tlb miss data (0b)1e3f4e51schedule uop (52)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst simd alu (9a)l1d cache writeback (a8)accfd5map dispatch bubble (d6)d9ddfetch restart (de)e0ea? simd retires (ee)f5f6f7f8fd
100430372300061254725100010001000398160301830373037241432895100010001000303730371110011000007331602326290100030383038303830383038
100430372300961254725100010001000398160301830373037241332895100010001000303730371110011000007321603326260100030383038303830383038
100430372300061254725100010001000398160301830373037241332895100010001000303730371110011000107321602226290100030383038303830383038
100430372400061254725100010001000398160301830373037241432895100010001000303730371110011000107321602326640100030383038303830383038
100430372300061254725100010001000398160301830373037241432895100010001000303730371110011000007531602226290100030383038303830383038
100430372300061254725100010001000398160301830373037241432895100010001000303730371110011000007321602226260100030383038303830383038
100430372300061254725100010001000398160301830373037241432895100010001000303730371110011000007321602326260100030383038303830383038
10043037230012187254725100010001000398160301830373037241432895100010001000303730371110011000007321602226290100030383038303830383038
100430372400061254725100010001000398160301830373037241432895100010001000303730371110011000007321602226290100030383038303830383038
100430372300061254725100010001000398160301830373037241432895100010001000303730371110011000007321603226260100030383038303830383038

Test 2: Latency 1->2

Code:

  fcvtzs d0, d0
  movi v0.16b, 1
  movi v1.16b, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03mmu table walk instruction (07)1e3a3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d cache writeback (a8)accfd5map dispatch bubble (d6)daddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
1020430037225000371295472510100100100001001000062642771601300180300373003728264032874510100200100002001000030037300371110201100991001001000010000710116011296330100001003003830038300383003830038
1020430037225000191295472510125100100001001000050042771601300180300373003728264032874510125200100002001000030037300371110201100991001001000010000710116011296330100001003003830038300383003830038
102043003722500084295472510100100100001001000050042771601300180300373003728264732874510100200100002001000030037300371110201100991001001000010003710116011296330100001003003830038300383003830038
102043003722400084295472510100100100001001000050042771601300180300373003728264032874510100200100002001000030037300371110201100991001001000010000710116011296330100001003003830038300383003830038
102043003722500061295472510100100100001001000050042771601300180300373003728264032874510100200100002001000030037300371110201100991001001000010000710116011296330100001003003830038300383003830038
10204300372250001492954725101251001000012510000500427716013001803003730037282640328745101002001000020010000300373003711102011009910010010000100107101160112963325100001003003830038300383003830038
102043003722400084295472510100100100001001000050042771601300180300373003728264032874510100200100002001000030037300371110201100991001001000010000712116011296330100001003003830038300383003830038
102043003722500084295472510100100100001001000050042771601300180300373003728264032874510125200100002001000030037300371110201100991001001000010000710116011296330100001003003830038300383003830038
1020430037225000168295474410130100100001001000050042771600300180300373003728264032874510252200100002001000030037300371110201100991001001000010000710116011296330100001003003830038300383003830038
1020430037224000797295472510100100100001251000062642771600300180300373003728264032874510100200100002001000030037300371110201100991001001000010000710116011296330100001003003830038300383003830038

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0037

retire uop (01)cycle (02)03191e1f3f4e51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)a9accfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
10024300372250006129547251001010100001010000504277160030018300373003728286328767100102010000201000030037300371110021109101010000100000640216222962910000103003830038300383003830038
10024300372240006129547251001010100001010000504277160030018300373003728286328767100102010000201000030037300371110021109101010000100000640216222962910000103003830038300383003830038
100243003722510886129547251001010100001010000504277160030018300373003728286328767100102010000201000030037300371110021109101010000100000640216222962910000103003830038300383003830038
100243003722500025129547251001010100001010000504277160030018300373003728286328767100102010000201000030037300371110021109101010000100000640216222962910000103003830038300383003830038
100243003722400025129547251001010100001010000504277160030018300373003728286328767100102010000201000030037300371110021109101010000100000640216252962910000103003830038300383003830038
10024300372250006129547251001010100001010000504277160130018300373003728286328767100102010000201000030037300371110021109101010000100000640216222962910000103003830038300383003830038
100243003722500015629547251001010100001010000504277160130018300373003728286328767100102010000201000030037300371110021109101010000100000640216222962910000103003830038300383003830038
100243003722500072629547251001010100001010000504277160130018300373003728286328767100102010000201000030037300371110021109101010000100000640216222962910000103003830038300383003830038
10024300372250006129547251001010100001010000504277160030018300373003728286328767100102010000201000030037300371110021109101010000100000640216222962910000103003830038300383003830038
10024300372250006129547251001010100001010000504277160030018300373003728286328767100102010000201000030037300371110021109101010000100000640216232962910000103003830038300383003830038

Test 3: throughput

Count: 8

Code:

  fcvtzs d0, d8
  fcvtzs d1, d8
  fcvtzs d2, d8
  fcvtzs d3, d8
  fcvtzs d4, d8
  fcvtzs d5, d8
  fcvtzs d6, d8
  fcvtzs d7, d8
  movi v8.16b, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03181e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)simd prf full (72)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)ld unit uop (a6)l1d cache writeback (a8)acc2branch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
80204200391560005125801081008000810080020500640132020020200392003999770699908012020080032200800322003920039118020110099100100800001000000011151181160020036800001002004020040200402004020040
80204200391550003025801081008000810080020500640132020020200392003999770699908012020080032200800322003920039118020110099100100800001000000011151180160020036800001002004020040200402004020040
802042003915501203025801081008000810080020500640132020020200392003999770699908012020080032200800322003920039118020110099100100800001000000011151180160020036800001002004020040200402004020040
80204200391550003025801081008000810080020500640132020020200392003999770699908012020080032200800322003920039118020110099100100800001000000011151180160020036800001002004020040200402004020040
80204200391560003025801081008000810080020500640132120020200392003999770699908012020080032200800322003920039118020110099100100800001000000011151180160020036800001002004020040200402004020040
80204200391550003025801081008000810080020500640132120020200392003999770699908012020080032200800322003920039118020110099100100800001000010011151180160020036800001002004020040200402004020040
80204200391550003025801081008000810080020500640132020020200392003999770699908012020080032200800322003920039118020110099100100800001000000011151180160020036800001002004020040200402004020040
80204200391550003025801081008000810080020500640132020020200392003999770699908012020080032200800322003920039118020110099100100800001000000011151180160020036800001002004020040200402004020040
80204200391610003025801081008000810080020500640132020020200392003999770699908012020080032200800322003920039118020110099100100800001000000011151180160020036800001002004020040200402004020040
80204200391550003025801081008000810080020500640132120020200392003999770699908012020080032200800322003920039118020110099100100800001000000011151180160020036800001002004020040200402004020040

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.2505

retire uop (01)cycle (02)03mmu table walk data (08)18191e1f3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acc2cfd5map dispatch bubble (d6)d9ddfetch restart (de)e0? simd retires (ee)? int retires (ef)f5f6f7f8fd
800242003915500000103258001010800001080000506400001200202003920039999631001980010208000020800002003920039118002110910108000010000000050201276112003680000102004020040200402004020040
80024200391550000068258001010800001080000506400000200202003920039999631001980010208000020800002003920039118002110910108000010000000050201160112003680000102004020040200402004020040
800242003915500048040258001010800001080000506400000200202003920039999631001980010208000020800002003920039118002110910108000010000000050201162112003680000102004020040200402004020040
800242003915500000705258001010800001080000506400000200202003920039999631001980010208000020800002003920039118002110910108000010000000050201160112003680000102004020040200402004020040
80024200391550000040258001010800001080000506400001200202003920039999631001980010208000020800002003920039118002110910108000010000000050201160112003680000102004020040200402004020040
80024200391550000040258001010800001080000506400000200202003920039999631001980010208000020800002003920039118002110910108000010000600050201160112003680000102004020040200402004020040
800242003915500012040258001010800001080000506400000200202003920039999631001980010208000020800002003920039118002110910108000010000000050201162112003680000102004020040200402004020040
80024200391650000040258001010800001080000506400001200202003920039999631001980010208000020800002003920039118002110910108000010000003050201160112003680000102004020040200402004020040
80024200391550000040258001010800001080000506400000200202003920039999631001980010208000020800002003920039118002110910108000010000000050201160112003680000102004020040200402004020040
80024200391560000040378001010800001080000506400000200202003920039999631001980010208000020800002003920039118002110910108000010000000050201160112003680000102004020040200402004020040