Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

FCVTZS (scalar, integer, D to W)

Test 1: uops

Code:

  fcvtzs w0, d0
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 3.000

Integer unit issues: 1.000

Load/store unit issues: 0.000

SIMD/FP unit issues: 2.000

retire uop (01)cycle (02)03191e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch simd uop (57)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map simd uop (7e)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst int alu (97)l1d cache writeback (a8)cfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
2004541400432530001000200020001800015225415412483274200020002000541541111001100007311611538100010001000542542542542542
2004541400642530001000200020001800005225415412483274200020002000541541111001100017311611538100010001000542542542542542
2004541400432530001000200020001800005225415412483274200020002000541541111001100007311611538100010001000542542542542542
2004541400432530001000200020001800005225415412483274200020002000541541111001100007311611538100010001000542542542542542
2004541400432530001000200020001800005225415412483274200020002000541541111001100007311611538100010001000542542542542542
2004541400432530001000200020001800005225415412483274200020002000541541111001100007311611538100010001000542542542542542
2004541400432530001000200020001800005225415412483274200020002000541541111001100007311611538100010001000542542542542542
2004541400432530001000200020001800005225415412483274200020002000541541111001100007311611538100010001000542542542542542
2004541500672530001000200020001800005225415412483274200020002000541541111001100007311611538100010001000542542542542542
2004541400432530001000200020001800005225415412483274200020002000541541111001100037311611538100010001000542542542542542

Test 2: Latency 1->2 roundtrip

Code:

  fcvtzs w0, d0
  fmov d0, x0
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 13.0038

retire uop (01)cycle (02)03mmu table walk data (08)18191e1f3a3f4f51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fl1d tlb access (a0)l1d tlb miss (a1)ld unit uop (a6)l1d cache writeback (a8)a9acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd0d5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
302041300389740000001300231194172540100101002000010000100200001000050062149791480103401300131300381300381254836126241301002001000220006200100022000613003813003811202011009910010100100001000010000000111131701161112953310021100001000010100130119130039130039130039130039
3020413003897400021001300231194172540100101002000010000100200001000050062149791480397201300131300381300381254837126241301002001000220006200100022000613003813003811202011009910010100100001000010000000111131701161112953310000100001000010100130039130039130039130076130100
302041300389740009001300231194172540100101002000010000100200001000050062149791480103401300131300381300381254836126241301002001000220006200100022000613003813003811202011009910010100100001000010000000111131801161112953410000100001000010100130039130039130039130039130039
302041300389740000001300231194172540100101002000010000100200001000050062149791480103411300131300381300381254836126242301002001000220006200100022000613007913003811202011009910010100100001000010000000111131801161112953310000100001000010100130039130039130039130039130039
302041300389740000001300511194172540100101002000010000100200001000050062149791480103401300131300381300381254836126242301002001000220006200100022000613003813003811202011009910010100100001000010000000000131012162212952510000100001000010100130039130039130039130039130039
3020413003897400012001300231194172540100101002000010000100200001000050062149791480103411300131300381300381254763126246301002001000020000200100002000013003813003811202011009910010100100001000010000000000131012162212952510000100001000010100130039130039130039130041130039
302041300389740000001300231194172540100101002000010000100200001000058162167071480103411300131300381300381254763126246301002001000020000200100002000013003813003811202011009910010100100001000010000000000131012162212952510000100001000010100130039130039130039130039130039
302041300389740009001300231194172540100101002000010000100200001000050062149791480103411300131300381300381254763126246301002001000020128200100002000013003813003811202011009910010100100001000010000000000131011162212952510000100001000010100130039130039130039130039130039
3020413003897400000013002311941725401001010020000100001002000010000500621497914801034113001413003813004012547625126246301002001000020000200100002000013003813004111202011009910010100100001000010000003000131012163212952510000100001000010100130039130039130039130063130041
3020413003897414056420801300231194172540100101002000010000100200001000050062149791480103401300131300381300401254763126246301002001000020000200100002000013003813003811202011009910010100100001000010000003000131012162312952710000100001000010100130039130039130040130039130039

1000 unrolls and 10 iterations

Result (median cycles for code): 13.0038

retire uop (01)cycle (02)03mmu table walk data (08)l2 tlb miss data (0b)181e1f3f4f51schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)60696b6d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)inst simd alu (9a)9fld unit uop (a6)l1d cache writeback (a8)a9acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)f5f6f7f8fd
3002413003897400090130023119417254001010010200001000010200001000050621497914800025013001301300381300381254983126268300102010000200002010000200001301161300391120021109101001010000101000000000012702161112952510000100001000010010130039130039130039130039130081
3002413003897400000130132119417254001010010200001000010200001000060621497914800933113001301300381300381254983126268300102010000200002010000200001300901300691120021109101001010000101000000000012701161212952510000100001000010010130039130039130039130039130039
3002413003897400000130023119417254001010010200001000010200001000050621497914800025013001301300381300381254983126268300102010000200002010000200001300491300411120021109101001010000101000000000012701161212952510000100001000010010130039130039130039130039130039
3002413003997300000130023119417254001010010200001000010200001000050621497914800025013001301300381300381254983126268300102010000200002010000200001301011300381120021109101001010000101000000000012701161112952510000100001000010010130039130039130039130039130039
30024130074974000001300231194172540018100112000010000102012110000506214979148000250130013013003913007412549931262683001020100002000020100002000013004713003811200211091010010100001010000770000012701161112952510000100001000010010130039130039130039130039130039
3002413003897401000130023119417254001010010200001000010200001000050621497914800025013001301300381300381254983126268300102010000200002010000200001300811300761120021109101001010000101000000000012701161112952510000100001000010010130039130039130039130039130039
3002413003897400000130023119443254001010010200001000010200001000050621497914800025013001301300381300381254983126268300102010000200002010000200001301001300411120021109101001010000101000000000012701161112952510000100001000010010130039130039130039130039130039
3002413003897400000130023119417254001010010200001000010201221000050621497914800849113001301300381300381254983126268300102010000200002010000200001300931300611120021109101001010000101000000000012701161112952510000100001000010010130039130039130039130039130039
3002413003897400000130023119417254001010010200001000010200001000050621497914800025013001301300381300381254983126268300102010000200002010000200001300491300381120021109101001010000101000010300012701161112952510000100001000010010130039130039130039130039130039
3002413004097400000130024119417254001010010200001000010200001000050621497914800025013001301300411300381254983126268300102010000200002010000200001300621300411120021109101001010000101000000000012701161112952510000100001000010010130039130039130039130039130039

Test 3: throughput

Count: 8

Code:

  fcvtzs w0, d8
  fcvtzs w1, d8
  fcvtzs w2, d8
  fcvtzs w3, d8
  fcvtzs w4, d8
  fcvtzs w5, d8
  fcvtzs w6, d8
  fcvtzs w7, d8
  mov x8, 9

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5005

retire uop (01)cycle (02)03191e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fl1d cache writeback (a8)acbranch cond mispred nonspec (c5)branch mispred nonspec (cb)cdcfd5map dispatch bubble (d6)ddfetch restart (de)e0? int output thing (e9)? simd retires (ee)? int retires (ef)f5f6f7f8fd
160204400623000032252401048010016000410016002050014401324002240041400411997761999216012020016003220016003240041400411180201100991008010010000111511731621400388000080000801004004240042400424004240042
160204400413000032252401048010016000410016002050014401324002240041400411997761999216012020016003220016003240041401291180201100991008010010000111511711612400388000080000801004004240042400424004240042
160204400413000632252401048010016000410016002050014401324002240041400411997761999216012020016003220016003240041400411180201100991008010010000111511711622400388000080000801004004240042400424004240042
16020440041300054932252401048010016000410016002050014401324002240041400411997761999216012020416003220016003240041400411180201100991008010010000111511721621400388000080000801004004240042400424004240042
160204400413000032252401048010016000410016002050014401324002240041400411997761999216012020016003220016003240041400411180201100991008010010000111511711622400388000080000801004004240042400424004240042
160204400413000032252401048010016000410016002050014401324002240041400411997761999216012020016003220016003240041400411180201100991008010010000111511721621400388000080000801004004240042400424004240042
160204400412990032252401048010016000410016002050014401324002240041400411997761999216012020016003220016003240041400411180201100991008010010000111511721622400388000080000801004004240042400424004240042
160204400413000032252401048010016000410016002050014401324002240041400411997761999216012020016003220016003240041400411180201100991008010010000111511721622400388000080000801004004240042400424004240042
160204400413000032252401048010016000410016002050014401324002240041400411997761999216012020016003220016003240041400411180201100991008010010000111511721622400388000080000801004004240042400424004240042
160204400413000032252401048010016000410016002050014401324002240041401271997761999216012020016003220016003240041400411180201100991008010010000111511731621400388000080000801004004240042400424004240042

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

retire uop (01)cycle (02)03l2 tlb miss data (0b)1e3f51schedule uop (52)schedule int uop (53)schedule simd uop (54)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)ldst uops in schedulers (5b)5f60696d6emap stall dispatch (70)map rewind (75)map stall (76)dispatch uop (78)map int uop (7c)map simd uop (7e)map int uop inputs (7f)map simd uop inputs (81)8283flush restart other nonspec (84)85inst all (8c)inst branch (8d)inst branch taken (90)inst branch cond (94)inst int alu (97)9fld unit uop (a6)l1d cache writeback (a8)acc2cfd0d2l1i cache miss demand (d3)d5map dispatch bubble (d6)d9dadbddfetch restart (de)e0? int output thing (e9)ea? simd retires (ee)? int retires (ef)f5f6f7f8fd
16002440055299004225240010800101600001016000050144000000400224004140041199963200211600102016000020160000400414004111800211091080010100000502400016160001374003880000080000800104004240042400424004240042
1600244004129900422524001080010160000101600005014400000040022400414004119996320021160010201600002016000040041400411180021109108001010000050200008160008174003880000080000800104004240042400424004240042
16002440041300004225240010800101600001016000050144000000400224004140041199963200211600102016000020160000400414004111800211091080010100000502000117162001784003880000080000800104004240042400424004240042
16002440041299007072524001080010160000101600005014400000140022400414004119996320021160010201600002016000040041400411180021109108001010020450200008160008174003880000080000800104004240042400424004240042
160024400413000042252400108001016000010160000501440000004002240041400411999632002116001020160000201600004004140041118002110910800101000005020000171600017174003880000080000800104004240042400424004240042
160024400413000042252400108001016000010160000501440000004002240041400411999632002116001020160000201600004004140041118002110910800101000005022010816010171240038800001580000800104004240042400424004240042
1600244004130000422524001080094160000101600005014400000140022400414004119996320021160010201600002016000040041400411180021109108001010000050200008160001764003880000080000800104004240042400424004240042
1600244004130000422524001080010160000101600005014400000040022400414004119996320021160010201600002016000040041400411180021109108001010000050220008160007134003880000080000800104004240042400424004240042
1600244004130000422524001080010160000101600005014400000040022400414004119996320021160010201600002016000040041400411180021109108001010000050200006160008174003880000080000800104004240042400424004240042
16002440041299004225240010800101600001016000050144000001400224004140041199963200211600102016000020160000400414004111800211091080010100000502200017160008174003880000080000800104004240042400424004240042